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| HD404669 Series Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit ADE-202-083B Rev. 3.0 Sept. 1999 Description The HD404669 Series microcomputers incorporate a DTMF generation circuit, two comparators, and a serial interface on chip. They also provide input and output pins with large current handling capacities. Thus they are 4-bit single-chip microcomputers that are optimal for use in multifunction telephones, cordless telephones, and other communications equipment. HD404669 Series microcomputers have a 32.768 kHz sub-oscillator for realtime clock use, providing a time counting facility, and a variety of power supply modes to reduce current drain. The HD407A4669 is a ZTATTM microcomputer with on-chip PROM that drastically shortens development time and ensures a smooth transition from debugging to mass production. (The PROM programming specifications are the same as for the 27256 type.) ZTATTM: Zero Turn-Around Time ZTAT is a trademark of Hitachi, Ltd. Features * 1,152-digit x 4-bit RAM * I/O pins: 47 High-current I/O pins (source: 10 mA max.): 4 High-current I/O pins (sink: 15 mA max.): 5 * Timer counters: 3 * Input capture: one 8-bit channel * Timer outputs: 2 (with PWM output capability) * Event input: 1 (edge-programmable) * Clock synchronous 8-bit serial interface: 1 * DTMF generation circuit * Comparator: 2 channels * System clock oscillator Ceramic oscillator, crystal oscillator, or external clock operation possible HD404669 Series * Subsystem clock oscillator 32.768 kHz crystal oscillator for realtime clock use * Interrupts External: 5 (including 3 edge-programmable) Internal: 4 * Subroutine stack: max. 16 levels including interrupts * Low-power modes: 4 * System clock division software switching (1/4, 1/8, 1/16, 1/32) * Instruction execution time Min. 1 s (fOSC = 4 MHz, 1/4 clock division) Min. 0.5 s (fOSC = 8 MHz, 1/4 clock division) * Operating voltage 1.8 V to 5.5 V 2.2 V to 5.5 V (ZTATTM) Ordering Information Type Mask ROM (standard version) Product Name HD404668 Model Name HD404668H ROM (Words) 8,192 RAM (Digits) 1,152 Package 64-pin plastic QFP (FP-64A) HD4046612 HD404669 HCD404669 Mask ROM (high-speed version) HD40A4668 HD4046612H HD404669H HCD404669 HD40A4668H 12,288 16,384 16,384 8,192 Chip *1 *2 64-pin plastic QFP (FP-64A) HD40A46612 HD40A4669 ZTATTM (high-speed version) Note: HD407A4669 HD40A46612H HD40A4669H HD407A4669H 12,288 16,384 16,384 1. ZTATTM chip shipment is not supported. 2. The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details. Cautions about Operation The mask ROM and ZTATTM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this data sheet. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, internal 2 HD404669 Series wiring patterns, etc. Users are therefore requested to confirm the operation of individual products by conducting evaluation tests under conditions equivalent to those in the actual application system. List of Functions Standard version HD404668 Highspeed version HD4046612 HD404669 HCD404669 Product name HD40A4668 HD40A46612 HD40A4669 ------ HD407A4669 ROM (Words) RAM (Digits) I/O Large-current I/O pins Timer / Counter Input capture Timer output Event input Serial interface DTMF generation circuit Comparator Interrupt External Internal Low-Power Dissipation Mode Stop mode Watch /mode Standby mode Subactive mode Main Oscillator Ceramic oscillation Crystal oscillation Sub oscillator Minimum instruction execution time Crystal oscillation Standard version 8,192 1,152 52 (max) 12,288 16,384 16,384 16,384PROM 4 ( Source 10mA max), 5 (Sink 15 mA max) 3 8 bit x 1 2 (PWM output possible) 1 (edge selection possible) 1 (8-bit clock syncronous) Available 2 5 (edge selection possible for 3) 4 4 Available Available Available Available 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz*, 8 MHz* 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 Mhz, 7.16 MHz*, 8 MHz* 32.768 kHz 1 s (fOSC = 4 MHz, 1/4 frequency division) 0.5 s (fOSC = 8 MHz, 1/4 frequency division) 1.8 to 5.5 64-pin plastic QFP (FP-64A) 1.8 to 5.5 Chip 2.2 to 5.5 64-pin plastic QFP (FP-64A) -20 to +75 High-speed version Operating voltage (V) Package Guaranteed operation temperature (C) -20 to +75 +75C Note: * Applies to high-speed versions (HD40A4668, HD40A46612, HD40A4669, HD407A4669). 3 HD404669 Series Pin Arrangement RD1/COMP1 RD0/COMP0 TONER TONEC VCC VTref SEL RA1 RA0 R93 R92 R91 R90 R83 51 R82 50 64 63 62 61 60 59 58 57 56 55 54 53 52 RE0/VCref TEST OSC1 OSC2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D9 D10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 49 48 47 46 45 44 43 42 R81 R80 R73 R72 R71 R70 R63 R62 R61 R60 R43 /SO1 R42 /SI1 R41 /SCK1 R40 /EVND R31 /TOC R32 /TOD R33 FP-64A 41 40 39 38 37 36 35 34 33 D12 /STOPC D13 /INT0 R00 /INT1 R01 /INT2 R02 /INT3 R03 /INT4 R10 R11 R12 R13 R20 R21 R22 R23 Top view 4 R30 D11 HD404669 Series Pad Arrangement HCD404669 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TYPE CODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 35 34 37 36 39 38 41 40 43 42 45 44 47 46 48 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TYPE CODE: HD404669 5 HD404669 Series Bonding Pad Coordinates HCD404669 Y TYPE CODE Chip center (X=0, Y=0) X Chip Size (X x Y): 4.34 x 4.01 (mm) Coordinates: Pad Center Home Point position: Chip Center Pad size (X x Y): 90 x 90 (m) Chip thickness: 400 (m) Pad Pad No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RE0 TESTN OSC1 OSC2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D9 D10 Coordinates X -1983 -1983 -1983 -1983 -1983 -1983 -1983 -1983 -1983 -1983 -1983 -1983 -1983 -1983 -1983 -1983 Y 1444 1252 1062 871 657 466 275 84 -108 -299 -490 -680 -871 -1062 -1253 -1444 Pad Pad No. Name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D11 D12 D13 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 Coordinates X Y Pad Pad No. Name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 R33 R32 R31 R40 R41 R42 R43 R60 R61 R62 R63 R70 R71 R72 R73 R80 Coordinates X 1983 1983 1983 1983 1983 1983 1983 1983 1983 1983 1983 1983 1983 1983 1983 1983 Y -1444 -1252 -1060 -867 -675 -483 -291 -99 93 285 478 670 862 1054 1246 1444 Pad Pad No. Name 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 R81 R82 R83 R90 R91 R92 R93 RA0 RA1 SEL V CC TONEC TONER VTREF RD0 RD1 Coordinates X 1587 1374 1161 948 735 522 309 93 -177 -329 -542 -755 -968 -1181 -1394 -1607 Y 1819 1819 1819 1819 1819 1819 1819 1819 1819 1819 1819 1819 1819 1819 1819 1819 -1607 -1819 -1394 -1819 -1181 -1819 -968 -755 -541 -329 -117 96 309 522 735 948 1161 1374 1587 -1819 -1819 -1819 -1819 -1819 -1819 -1819 -1819 -1819 -1819 -1819 -1819 -1819 6 HD404669 Series Pin Description Pin Number Item Power supply Test Reset Oscillator Symbol VCC GND TEST RESET OSC1 FP-64A, chip 59 8 2 5 3 I/O - - I I I Function Applies power voltage Connected to ground Used for factory testing only: Connect this pin to V CC Resets the MCU Input/output pins for the internal oscillator circuit: Connect them to a ceramic oscillator ,crystal oscillator or connect OSC 1 to an external oscillator circuit OSC2 X1 4 6 O I Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to V CC and leave the X2 pin open. X2 Port D0-D5, D9-D11 7 9-17 O I/O Input/output pins addressed by individual bits; D0 to D3 are source high-current input/output pins. A maximum 10 mA current can be supplied to each pin. D4, D5, and D9 to D11 are sink high-current input/output pins. A maximum 15 mA current can be supplied to each pin. D12 , D13 R00-R4 3, R60-RA 1 RD 0, RD1, RE0 Interrupt Stop clear Serial interface INT0, INT1, INT2-INT4 STOPC SCK1 SI 1 SO 1 Timer TOC, TOD EVND DTMF TONER TONEC VTref 18, 19 20-57 63, 64, 1 19-23 18 37 38 39 35, 34 36 61 60 62 I I/O I I I I/O I O O I O O - Input pins addressable by individual bits Input/output pins addressable in 4-bit units Input pins addressable in 4-bit units Input pins for external interrupts Input pin for transition from stop mode to active mode Serial interface clock input/output pin Serial interface receive data input pin Serial interface transmit data output pin Timer output pins Event input pin Output pin for DTMF row signals Output pin for DTMF column signals Reference voltage pin for DTMF signals. Voltage conditions are: VCC VTref GND 7 HD404669 Series Pin Number Item Voltage comparator Symbol COMP0, COMP1 VCref Frequency division ratio selection SEL FP-64A, chip 63, 64 1 58 I/O I - I Function Comparator analog input pins. Analog input pin threshold voltage reference level power supply pin. Pin that selects the system clock division ratio immediately after a reset and when returning from stop mode to active mode. Connect to Vcc voltage to select division-by-4, or to GND potential to select division-by-32. 8 HD404669 Series Block Diagram RESET TEST STOPC OSC1 OSC2 X1 X2 VCC GND SEL HMCS400 CPU ROM INT0 INT1 INT2 INT3 INT4 RAM External interrupt control circuit 8-bit timer A (free-running timer) RE RD RA port port port R9 port R8 port R7 port R6 port R4 port R3 port R2 port R1 port R0 port D0 D1 D2 D3 D4 D5 D9 D10 D11 D12 D13 D port R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R60 R61 R62 R63 R70 R71 R72 R73 R80 R81 R82 R83 R90 R91 R92 R93 RA0 RA1 RD0 RD1 RE0 TOC 8-bit timer C EVND TOD SCK1 SI1 SO1 VTref TONER TONEC VCref COMP0 COMP1 8-bit timer D Synchronous 8-bit serial interface DTMF generation circuit Comparator : Data bus : Signal line 9 HD404669 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. ROM address $0000 $000F $0010 Zero page subroutine area (64 words) Vector addresses (16 words) ROM address $0000 $0001 $0002 $0003 $0004 $0005 $0006 Pattern area (4,096 words) JMPL instruction (Jump to reset, stop mode clearance routine) JMPL instruction (Jump to INT0 interrupt handling routine) JMPL instruction (Jump to INT1 interrupt handling routine) JMPL instruction (Jump to timer A interrupt handling routine) JMPL instruction (Jump to INT2 interrupt handling routine) JMPL instruction (Jump to timer C, INT3 interrupt handling routine) JMPL instruction (Jump to timer D, INT4 interrupt handling routine) JMPL instruction (Jump to serial 1 routine) $003F $0040 $0007 $0008 $0FFF $1000 HD404668/HD40A4668 program area (8,192 word) $0009 $000A $000B $000C $000D HD4046612/HD40A46612 program area (12,288 words) $1FFF $2000 $000E $000F $2FFF $3000 HD404669/HD40A4669/ HCD404669/HD407A4669 program area (16,384 words) $3FFF Figure 1 ROM Memory Map Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$1FFF: HD404668, HD40A4668; $0000-$2FFF: HD4046612, HD40A46612; $0000-$3FFF: HD404669, HD40A4669, HD407A4669, HCD404669): Used for program coding. 10 HD404669 Series RAM Memory Map The MCU contains a RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same RAM memory space. The RAM memory map is shown in figure 2 and described below. RAM-Mapped Register Area ($000-$03F): * Interrupt Control Bits Area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. * Special Function Register Area ($004-$01F, $024-$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timers, DTMF, comparator, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register Flag Area ($020-$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. 11 HD404669 Series RAM address $000 RAM-mapped register area RAM address $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F Interrupt control bit area $040 $050 Memory registers (16 digits) Port mode register A Serial mode register 1A Serial data register 1L Serial data register 1U Timer mode register A Not used Miscellaneous register Timer mode register C1 Timer C Timer mode register D1 Timer D Not used Timer mode register C2 Timer mode register D2 Not used Compare data register Compare enable register Tone generator mode register Tone generator control register (PMRA) (SM1A) (SR1L) (SR1U) (TMA) W W R/W R/W W Not used $090 *1 Data (464 digits x 2) V = 0 (bank = 0) V = 1 (bank = 1) $260 Data (144 digits) $2F0 $3C0 Stack area (64 digits) $3FF Not used (MIS) (TMC1) (TRCL/TWCL) (TRCU/TWCU) (TMD1) (TRDL/TWDL) (TRDU/TWDU) (TMC2) (TMD2) (CDR) (CER) (TGM) (TGC) W W R/W R/W W R/W R/W R/W R/W R W W W *2 *2 R : Read only W : Write only R/W : Read/Write Not used Register flag area Port mode register B Port mode register C Detection edge select register 1 Detection edge select register 2 Serial mode register 1B System clock select register 1 System clock select register 2 Not used Data control register D0 to D3 Data control register D4 to D5 Data control register D9 to D11 Not used Data control register R0 Data control register R1 Data control register R2 Data control register R3 Data control register R4 Not used Data control register R6 Data control register R7 Data control register R8 Data control register R9 Data control register RA Not used (V) R/W (PMRB) (PMRC) (ESR1) (ESR2) (SM1B) (SSR1) (SSR2) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR6) (DCR7) (DCR8) (DCR9) (DCRA) W W W W W W W W W W W W W W W W W W W W Note : *1. There are two data areas, V = 0 (bank 0) and V = 1 (bank 1) $090 Data (464 digits) V=0 (bank = 0) $25F Data (464 digits) V=1 (bank = 1) V register *2. Two registers are mapped onto the same address ($00E, $00F, $011, $012) $00E $00F $011 $012 Timer read register CL Timer read register CU Timer read register DL Timer read register DU (TRCL) (TRCU) (TRDL) (TRDU) R R R R Timer write register CL Timer write register CU Timer write register DL Timer write register DU (TWCL) (TWCU) (TWDL) (TWDU) W W W W Figure 2 RAM Memory Map 12 HD404669 Series RAM address Bit 3 $000 IM0 (INT0 interrupt mask) Bit 2 IF0 (INT0 interrupt request flag) IFTA (Timer A interrupt request flag) IFTC (Timer C interrupt request flag) IFS1 (Serial 1 interrupt request flag) Bit 1 RSP (Reset stack pointer) IM1 (INT1 interrupt mask) Bit 0 IE (Interrupt enable flag) IF1 (INT1 interrupt request flag) IMTA $001 (Timer A interrupt mask) IMTC $002 (Timer C interrupt mask) IMS1 (Serial 1 interrupt mask) Not used Not used $003 IMTD (Timer D interrupt mask) IFTD (Timer D interrupt request flag) Interrupt control bits area RAM address Bit 3 $020 DTON (DTON flag) Bit 2 Bit 1 WDON (Watchdog on flag) ICEF (Input capture error flag) IM2 (INT2 interrupt mask) IM4 (INT4 interrupt mask) Bit 0 LSON (Low speed on flag) ICSF (Input capture status flag) IF2 (INT2 interrupt request flag) IF4 (INT4 interrupt request flag) Not used $021 RAME (RAM enable flag) IM3 (INT3 interrupt mask) Not used $022 IF3 (INT3 interrupt request flag) $023 Not used Not used Register flag area IF IM IE SP : Interrupt Request Flag : Interrupt Mask : Interrupt Enable Flag : Stack Pointer Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas 13 HD404669 Series Bits in the interrupt control bits area and register flag area can be set and reset by the SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not affected by any other instructions. The following restrictions apply to individual bits. SEM/SEMD IE IM LSON IF ICSF ICEF RAME RSP WDON DTON Not used Allowed REM/REMD Allowed TM/TMD Allowed Not executed Not executed Allowed Not executed in active mode Used in subactive mode Not executed Allowed Allowed Not executed Allowed Not executed Allowed Inhibited Inhibited Allowed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 14 HD404669 Series Bit 3 Bit 2 Bit 1 Bit 0 $000 $001 Interrupt control bits area $002 $003 R43/SO1 R42/SI1 $004 $005 R41/SCK1 Serial transfer clock speed selection 1 $006 Serial data register 1 (lower) $007 Serial data register 1 (upper) Clock source setting (timer A) Timer A/time base $008 $009 $00A $00B $00C MOS pull-up/pull-down control R43/SO1 PMOS control Interrupt frame period selection Clock source setting (timer C) $00D Reload on/off $00E Timer C register (lower) $00F Timer C register (upper) $010 Reload on/off Clock source setting (timer D) $011 Timer D register (lower) $012 Timer D register (upper) $013 $014 Timer C output mode setting $015 Input capture selection Timer D output mode setting $016 $017 COMP1 comparison result COMP0 comparison result $018 Comparator operation selection Comparator selection $019 TONEC output frequency TONER output frequency $01A TONEC output TONER output DTMF enable $01B $01C $01D $01E $01F $020 $021 Register flag area $022 $023 R02/INT3 $024 R01/INT2 R00/INT1 R03/INT4 D13/INT0 $025 D12/STOPC R40/EVND INT3 detection edge selection INT2 detection edge selection $026 EVND detection edge selection INT4 detection edge selection $027 SO1 idle High/Low setting Serial clock selection $028 DTMF speed setting $029 *2 *1 $02A DTMF speed setting OSC frequency division ratio switching $02B Port D0DCR Port D3DCR Port D2DCR Port D1DCR $02C Port D5DCR Port D4DCR $02D Port D11DCR Port D10DCR Port D9DCR $02E $02F Port R03DCR Port R02DCR Port R01DCR Port R00DCR $030 Port R13DCR Port R12DCR Port R11DCR Port R10DCR $031 Port R23DCR Port R22DCR Port R21DCR Port R20DCR $032 Port R33DCR Port R32DCR Port R31DCR Port R30DCR $033 Port R43DCR Port R42DCR Port R41DCR Port R40DCR $034 $035 Port R63DCR Port R62DCR Port R61DCR Port R60DCR $036 Port R73DCR Port R72DCR Port R71DCR Port R70DCR $037 Port R83DCR Port R82DCR Port R81DCR Port R80DCR $038 Port R93DCR Port R92DCR Port R91DCR Port R90DCR $039 Port RA1DCR Port RA0DCR $03A $03B $03C $03D $03E Bank setting $03F PMRA SM1A SR1L SR1U TMA MIS TMC1 TRCL/TWCL TRCU/TWCU TMD1 TRDL/TWDL TRDU/TWDU TMC2 TMD2 CDR CER TGM TGC PMRB PMRC ESR1 ESR2 SM1B SSR1 SSR2 DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR6 DCR7 DCR8 DCR9 DCRA V : Not used *1: 32kHz oscillation stop setting *2: 32kHz frequency division ratio switching Figure 5 Special Function Register Area 15 HD404669 Series Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. RAM address $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F MR MR MR MR MR MR MR MR MR MR MR MR MR MR MR MR (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) $3C0 Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 (b) Stack area PC13 to PC0 : Program counter ST : Status flag CA : Carry flag Bit 3 $3FC $3FD $3FE $3FF ST PC10 CA PC3 Bit 2 PC13 PC9 PC6 PC2 Bit 1 PC12 PC8 PC5 PC1 Bit 0 PC11 PC7 PC4 PC0 $3FF (a) Memory registers Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position 16 HD404669 Series Data Area ($090-$2EF): 464 digits from $090 to $25F have two banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $026 to $2EF is accessed without setting the bank register. Bank register (V: $03F) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 -- -- 0 0 R/W V0 Not used Not used Not used V0 0 1 Bank area selection Bank 0 is selected Bank 1 is selected Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected. Figure 7 Bank Register (V) Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 17 HD404669 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below. 3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Initial value: 1, R/W not possible 13 (PC) 9 Stack pointer Initial value: $3FF, R/W not possible 1 1 1 1 5 (SP) 0 (ST) 0 (SPX) 0 (Y) 0 (X) 0 0 (W) 0 (A) 0 0 Program counter Initial value: $0000, R/W not possible Figure 8 Registers and Flags Accumulator (A) and B Register (B): A and B are 4-bit registers, and are used to hold the results of ALU (arithmetic and logical unit) operations and to transfer data between memory, I/O ports, and other registers. 18 HD404669 Series W Register (W), X Register (X), and Y Register (Y): W is a 2-bit register and X and Y are 4-bit registers. These registers are used in RAM register indirect addressing. The Y register is also used in D port addressing. SPX Register (SPX) and SPY Register (SPY): The SPX and SPY registers are 4-bit registers used to supplement the X and Y registers. Carry Flag (CA): CA is a 1-bit flag that stores ALU overflow generated by an arithmetic operation. CA is set to 1 when an overflow is generated, and is cleared to 0 after operations in which no overflow occurred. CA is also affected by the carry set/carry clear instructions (SEC and REC), and by the rotate with carry instructions (ROTL and ROTR). During interrupt handling, CA is saved on the stack, and is restored from the stack by the RTNI instruction. (but is not affected by the RTN instruction) Status Flag (ST): ST is a 1-bit flag that stores the results of arithmetic instructions, compare instructions, and bit test instructions, and is used as the branch condition for the BR, BRL, CAL, and CALL conditional branch instructions. The contents of the ST flag are held until the next arithmetic, compare, bit test, or conditional branch instruction is executed. After the execution of a conditional branch instruction, the value of ST is set to 1 without regard to the condition. During interrupt handling, ST is saved on the stack, and is restored from the stack by the RTNI instruction. (but is not affected by the RTN instruction) Program Counter (PC): The PC is a 14-bit counter that indicates the ROM address of the next instruction the CPU will execute. Stack Pointer (SP): The SP is a 10-bit register that indicates the RAM address of the next stack frame in the stack area. The SP is initialized to $3FF by a reset. The SP is decremented by 4 by a subroutine call or by interrupt handling, and is incremented by 4 when the saved data has been restored by a return instruction. The upper 4 bits of the SP are fixed at 1111; the maximum number of stack levels is thus 16. In addition to the reset method described above, the SP can also be initialized to $3FF by clearing the reset stack pointer (RSP) in the interrupt control bits area with a RAM bit manipulation instruction, i.e., REM or REMD. 19 HD404669 Series Reset The MCU can be reset by setting the RESET pin high or by setting the STOPC pin low*. When power is first applied, or when clearing subactive mode, watch mode, or stop mode, the RESET input must be held for at least tRC to assure that the oscillation stabilization time (tRC) condition is fulfilled. Similarly, the STOPC pin input must held for at least tRC when clearing stop mode with a STOPC pin input to assure that the oscillator stabilizes. In all other cases, the MCU is reset by a RESET input that is held for at least two instruction execution cycles. Table 1 lists the section of the MCU that are initialized by a reset and the initial values. Note: * The STOPC pin reset is only effective in stop mode. 20 HD404669 Series Table 1 Initial Values After MCU Reset Item Program counter Status flag Stack pointer Interrupt flags/mask Interrupt enable flag Interrupt request flag Interrupt mask I/O Port data register Data control register Data control register Data control register Data control register Data control register Port mode register A Port mode register B Port mode register C bits 3, 1, 0 Detection Edge select registers 1 and 2 Timer/ counters, serial interface Timer mode register A Abbr. (PC) (ST) (SP) (IE) (IF) (IM) (PDR) (DCD0) (DCD1) (DCD2) (DCR0-DCR4, DCR6-DCR9) (DCRA) (PMRA) (PMRB) (PMRC3, PMRC1, PMRC0) (ESR1, 2) (TMA) Initial Value $0000 1 $3FF 0 0 1 All bits 1 0000 --00 0000000 --00 --00 0000 00Refer to description of port mode register A Refer to description of R port Refer to description of port mode register C Contents Indicates program execution point from start address of ROM area Enables conditional branching Stack level 0 Inhibits all interrupts Indicates there is no interrupt request Prevents (masks) interrupt requests Enables output at level 1 Turns output buffer off (to high impedance) 0000 0000 Refer to description of interrupts Refer to description of timer mode register A section Timer mode register C1 Timer mode register C2 Timer mode register D1 Timer mode register D2 Serial mode register 1A Serial mode register 1B Prescaler S Prescaler W Timer counter A Timer counter C Timer counter D (TMC1) (TMC2) (TMD1) (TMD2) (SM1A) (SM1B) (PSS) (PSW) (TCA) (TCC) (TCD) 0000 -000 0000 0000 0000 --X0 $000 $00 $00 $00 $00 Refer to description of timer mode register C1 Refer to description of timer mode register C2 Refer to description of timer mode register D1 Refer to description of timer mode register D2 Refer to description of serial mode register 1A Refer to description of serial mode register 1B Refer to description of prescalers Refer to description of prescalers Refer to description of timer A Refer to description of timer C Refer to description of timer D 21 HD404669 Series Item Timer/ counters, serial interface Timer write register C Abbr. (TWCU, L) Initial Value $X0 Contents Refer to description of timer write register C Timer write register D Serial data register 1 Octal counter DTMF Tone generator mode register Tone generator control register (TWDU, L) (SR1U, L) (OC1) (TGM) (TGC) (CDR) (CER) (LSON) (WDON) (DTON) (ICSF) (ICEF) (MIS) (SSR12 -SSR10) (SSR2) (V) $X0 $XX 000 0000 000 --XX 0-00 0 0 0 0 0 0000 000 0000 - - -0 Refer to description of timer write register D Refer to description of serial data register 1 Refer to description of serial interface Refer to description of tone generator mode register Refer to description of tone generator control register Refer to description of compare data register Refer to description of compare enable register Refer to description of operating modes Refer to description of timer C Refer to description of operating modes Refer to description of timer D Refer to description of timer D Refer to description of operating modes and pull-up and pull-down MOS transistor control. Refer to description of internal oscillator circuit and system clock select register 1 and 2 Refer to description of internal oscillator circuit and system clock select register 1 and 2 Refer to description of RAM memory map Comparator Compare data register Compare enable register Bit registers Low speed on flag Watchdog timer on flag Direct transfer on flag Input capture status flag Input capture error flag Others Miscellaneous register System clock select register 1 bits 2 to 0 System clock select register 2 Bank register Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist. Item Carry flag Abbr. (CA) Status After Cancel-lation of Stop Mode by STOPC Input Pre-stop-mode values are not guaranteed; values must be initialized by program Status After all Other Types of Reset Pre-MCU-reset values are not guaranteed; values must be initialized by program Accumulator B register W register X/SPX register Y/SPY register RAM RAM enable flag Port mode register C bit 2 System clock select register 1 bit 3 (A) (B) (W) (X/SPX) (Y/SPY) Pre-stop-mode values are retained (RAME) (PMRC2) (SSR13) 1 Pre-stop-mode values are retained 0 0 22 HD404669 Series Interrupts The MCU has 9 interrupt sources: five external signals (INT0 , INT1, INT 2-INT 4), three timer/ counters (timers A, C, and D), serial interface (Serial 1). An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. As vector addresses are shared by interrupt sources timer C and INT3, and timer D and INT4, so the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 9 interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt RESET, STOPC* INT0 INT1 Timer A INT2 Timer C, INT3 Timer D, INT4 Serial 1 Priority -- 1 2 3 4 5 6 7 Vector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E Note: * The STOPC interrupt request is valid only in stop mode. 23 HD404669 Series $000, 0 IE $000, 2 INT0 interrupt IF0 $000, 3 IM0 $001, 0 INT1 interrupt IF1 $001, 1 IM1 $001, 2 Timer A interrupt IFTA $001, 3 IMTA $002, 2 Timer C interrupt IFTC $002, 3 IMTC $003, 0 Timer D interrupt IFTD $003, 1 IMTD $003, 2 Serial 1 interrupt IFS1 $003, 3 IMS1 $022, 0 IF2 $022, 1 IM2 $022, 2 IF3 $022, 3 IM3 $023, 0 IF4 $023, 1 IM4 INT4 interrupt INT3 interrupt INT2 interrupt Priority controller Vector address Interrupt request Figure 9 Interrupt Control Circuit 24 HD404669 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Cuntrol Bit IE IF0 . IM0 IF1 . IM1 IFTA . IMTA IF2 . IM2 IFTC . IMTC + IF3 . IM3 IFTD . IMTD + IF4 . IM4 IFS1 . IMS1 INT0 1 1 * * * * * * INT1 1 0 1 * * * * * Timer A 1 0 0 1 * * * * INT2 1 0 0 0 1 * * * Timer C or INT3 1 0 0 0 0 1 * * Timer D or INT4 1 0 0 0 0 0 1 * Serial 1 1 0 0 0 0 0 0 1 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a 2-cycle instruction. Execution of instruction at start address of interrupt routine Figure 10 Interrupt Sequence 25 HD404669 Series Power on RESET = "1"? Yes No Yes Interrupt request? No No IE = 1? Yes MCU reset Execute instruction Accept interrupt IE Stack Stack Stack Yes 0 (PC) (CA) (ST) PC (PC)+1 PC $0002 INT0 interrupt? No Yes PC $0004 INT1 interrupt? No Yes PC $0006 Timer A interrupt? No Yes PC $0008 INT2 interrupt? No Yes PC $000A Timer C or INT3 interrupt? No Yes PC $000C Timer D or INT4 interrupt? No PC $000E (Serial 1 interrupt) Figure 11 Interrupt Processing Flowchart 26 HD404669 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE 0 1 Interrupt Enabled/Disabled Disabled Enabled External Interrupt Request Flags (IF0-IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling edge of signals input to INT0 and INT1, and IF2-IF4 are set at the rising or falling edge of signals input to INT 2-INT 4, as listed in table 5. The INT2-INT4 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Detection edge selection register 1 (ESR1: $026) Bit Initial value Read/Write Bit name 3 0 W ESR13 2 0 W ESR12 1 0 W ESR11 0 0 W ESR10 ESR13 0 ESR12 0 1 INT3 detection edge No detection Falling-edge detection Rising-edge detection Falling/Rising-edge detection ESR11 0 ESR10 0 1 INT2 detection edge No detection Falling-edge detection Rising-edge detection Falling/Rising-edge detection 1 0 1 1 0 1 Figure 12 Detection Edge Selection Register 1 (ESR1) 27 HD404669 Series Detection edge selection register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W ESR22 1 0 W ESR21 0 0 W ESR20 ESR23 0 ESR22 0 1 EVND detection edge No detection Falling-edge detection Rising-edge detection Falling/Rising-edge detection ESR21 0 ESR20 0 1 INT4 detection edge No detection Falling-edge detection Rising-edge detection Falling/Rising-edge detection 1 0 1 1 0 1 Figure 13 Detection Edge Selection Register 2 (ESR2) Table 5 External Interrupt Request Flags (IF0-IF4: $000, $001, $022, $023) IF0-IF4 0 1 Interrupt Request No Yes External Interrupt Masks (IM0-IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0-IM4: $000, $001, $022, $023) IM0-IM4 0 1 Interrupt Request Enabled Disabled (masked) 28 HD404669 Series Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A, C, D Interrupt Request Flags (IFTA: $001, Bit 2, IFTC: $002, Bit 2, IFTD: $003, Bit 0) Timer A, C, D Interrupt Request Flags (IFTA, IFTC, IFTD) 0 1 Interrupt Request No Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A, C, D Interrupt Masks (IMTA: $001, Bit 3, IMTC: $002, Bit 3, IMTD: $003, Bit 1) Timer A, C, D Interrupt Masks (IMTA, IMTC, IMTD) 0 1 Interrupt Request Enabled Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 7. Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 8. Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling of signals input to EVND when the input capture function is used, as listed in table 7. Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 8. Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 9. Table 9 Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2) IFS1 0 1 Interrupt Request No Yes 29 HD404669 Series Serial 1 Interrupt Mask (IMS1: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial 1 interrupt request flag, as listed in table 10. Table 10 Serial 1 Interrupt Mask (IMS1: $003, Bit 3) IMS1 0 1 Interrupt Request Enabled Disabled (masked) 30 HD404669 Series Operating Modes The MCU has five operating modes as shown in table 11. The operations in each mode are listed in table 12. Transitions between operating modes are shown in figure 14. Table 11 Operating Modes and Clock Status Mode Name Active Activation method RESET cancellation, interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) System oscillator Subsystem oscillator Cancellation method Operation Standby SBY instruction Stop STOP instruction when TMA3 = 0 Watch STOP instruction when TMA3 = 1 STOP/SBY instruction in subactive mode (except when direct transition is specified) Subactive*2 INT0 or timer A interrupt request from watch mode when LSON = 1 Status Operation Stopped Stopped Stopped Operation RESET input, STOP/SBY instruction Operation *1 Operation RESET input, INT0 or timer A interrupt request Operation RESET input, STOP/SBY instruction RESET input, RESET input, interrupt STOPC input request Notes: 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029). 2. Subactive mode is an optional function; specify it on the function option list. 31 HD404669 Series Table 12 Operations in Low-Power Dissipation Modes Function CPU RAM Timer A Timer C Timer D Serial interface 1 DTMF Comparator I/O Stop Mode Reset Retained Reset Reset Reset Reset Reset Reset Reset (highimpedance) Notes: 1. When a clock is input in external clock mode, transmit/receive operations are performed, but interrupt operations are halted. 2. Subactive mode is a function option, and should be specified in the function option list. Watch Mode Retained Retained Operation Stopped Stopped Stopped *1 Reset Stopped Retained Standby Mode Retained Retained Operation Operation Operation Operation Operation Stopped Retained Subactive Mode*2 Operation Operation Operation Operation Operation Operation Reset Operation Operation 32 HD404669 Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR13 = 0) RAME = 0 RESET1 RAME = 1 RESET2 STOPC STOPC Active mode STOP fOSC: fX: o CPU : o CLK : o PER : Oscillate Oscillate Stop fcyc fcyc SBY Interrupt fOSC: fX: o CPU : o CLK : o PER : Oscillate Oscillate fcyc fcyc fcyc (TMA3 = 0) fOSC: fX: o CPU : o CLK : o PER : Stop Oscillate Stop Stop Stop Standby mode (TMA3 = 0, SSR13 = 1) STOP fOSC: fX: o CPU : o CLK : o PER : Stop Stop Stop Stop Stop Watch mode (TMA3 = 1) (TMA3 = 1, LSON = 0) fOSC: fX: o CPU : o CLK : o PER : Oscillate Oscillate Stop fW fcyc SBY Interrupt fOSC: fX: o CPU : o CLK : o PER : Oscillate Oscillate fcyc fW fcyc STOP INT0, timer A fOSC: fX: o CPU : o CLK : o PER : Stop Oscillate Stop fW Stop *2 Main oscillation frequency Subactive Suboscillation frequency STOP mode (TMA3 = 1, LSON = 1) for time-base fOSC: Stop fOSC: Stop *3 fcyc: fOSC/4, fOSC/8, fOSC/16 or Oscillate Oscillate fX: fX: fOSC/32 (selected by software) INT0, o CPU : fSUB o CPU : Stop fSUB: fX/8 or fX/4 timer A o CLK : fW o CLK : fW (software selectable) o PER : fSUB o PER : Stop fW: fX/8 o CPU : System clock o CLK : Clock for time-base Notes: 1. STOP/SBY (DTON = 1, LSON = 0) o PER : Peripheral functions clock 2. STOP/SBY (DTON = 0, LSON = 0) LSON: Low speed on flag 3. STOP/SBY (DTON = Don't care, LSON = 1) DTON: Direct transfer on flag fOSC: fX: *1 Figure 14 MCU Status Transitions 33 HD404669 Series Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC1 and OSC2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. (Interrupts, timers, the serial interface, and other peripheral functions continue to operate. The exception is the comparator, which is halted.) The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. Figure 15 shows a flowchart of MCU operation. Stop mode Standby mode Watch mode No RESET=1? RESET=1? Yes No No No IFTA * IMTA=1? Yes No No IF0 * IM0=1? Yes No Yes STOPC=0? Yes RAME=1 RAME=0 IF1 * IM1=1? Yes * IF2*IM2 = 1? Yes * IFTC*IMTC + IF3*IM3=1? Yes * No IFTD*IMTD + IF4*IM4=1? Yes * No No IFS1*IMS1=1 System clock oscillator started Next instruction execution MCU reset No IF =1, IM=0, IE =1? Yes Next instruction execution Interrupts enabled System clock oscillator started Yes * Note: * Only when clearing from standby mode. Figure 15 MCU Operation Flowchart 34 , HD404669 Series Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. For the X1 and X2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register 1 (SSR1: $029; operating: SSR13 = 0, stop: SSR3 = 1) (figure 24). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 40). Stop mode is cleared by a RESET or STOPC* input. The RESET or STOPC input must be held for at least the oscillation stabilization time (t RC) as shown in figure 16. (refer to the "AC Characteristics" section.) In either of these cases, the MCU will start program execution from the program start address (location 0). However, the value of the RAM enable flag (RAME: $021,3) will be different in these cases. In particular, RAME will be set to 0 for a RESET input and will be set to 1 for a STOPC input. Also note that while a RESET input is effective in all MCU modes, STOPC is only effective in stop mode, and is ignored in all other modes. If a program needs to determine if stop mode was cleared by a STOPC input (for example, if the program intends to use the contents of RAM that were stored before stop mode was entered after returning to active mode) the program should test the RAM enable flag with a TEST instruction at the start of the program. Note: * If stop mode is to be cleared by a S TOP C input, applications should set bit 2 of port mode register C (PMRC) to 1 (PMRC2 = 1) before switching to stop mode. Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution (at least equal to oscillation stabilization time tRC) Figure 16 Timing of Stop Mode Cancellation Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator, but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or by executing a STOP/SBY instruction while LSON is set to 1 or DTON is cleared to 0 in subactive mode. Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC ) for an INT 0 interrupt, as shown in figures 17 and 18. 35 HD404669 Series Operation during mode transition is the same as that at standby mode cancellation (figure 15). Oscillation stabilization time Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation tRC (During the transition from watch mode to active mode only) T T TX T: Interrupt frame period t RC : Oscillation stabilization time Note: If the time from the fall of the INT0 signal until the interrrupt is accepted and active mode is entered is designated Tx, then Tx will be in the following range: T + tRC < Tx < 2T + tRC Figure 17 Interrupt Frame 36 HD404669 Series Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions other than the DTMF generation circuit operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. The CPU instruction execution speed can be selected as 244 s or 122 s by setting bit 2 (SSR12) of the system clock select register (SSR1: $029). Note that the SSR12 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, CLK is applied to timer A and the INT0Icircuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame periods (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, the timer-A/ INT0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name MIS3 3 0 W MIS3 MIS2 2 0 W MIS2 MIS1 0 1 0 W MIS1 MIS0 0 0 0 W MIS0 T*1 tRC * 1 Oscillation circuit conditions External clock input Buffer control. See figure 37 in the pull-up and pull-down MOS transistor control section 0.24414 ms 0.12207 ms 0.24414 ms* 2 0 1 1 1 0 1 15.625 ms 7.8125 ms 62.5 ms Not used 31.25 ms Not used Ceramic oscillator Crystal oscillator -- Notes: 1. Values of T and tRC when a 32.768-kHz crystal oscillator is used to pins x1 and x2. 2. The value is applied only when direct transfer operation is used. Figure 18 Miscellaneous Register (MIS) 37 HD404669 Series Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: * Set LSON to 0 and DTON to 1 in subactive mode. * Execute the STOP or SBY instruction. * The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19). Notes: 1. The DTON flag can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode: tRC < TD < T + tRC STOP/SBY instruction execution Subactive mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T TD Interrupt frame period T: t RC : Oscillation stabilization time TD : Direct transition time t RC MCU internal processing time Oscillation stabilization time Active mode Figure 19 Direct Transition Timing MCU Operation Sequence: The MCU operates in the sequence shown in figure 20. It is reset by an asynchronous RESET input, regardless of its status. With the IE flag cleared and an interrupt request flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt request flags are cleared or all interrupts are masked. 38 HD404669 Series STOP/SBY instruction IF = 1 and IM = 0? No Yes Standby/watch mode Stop mode No IE = 0 * No IF = 1 and IM = 0? Interrupt service routine No STOPC = 0? Yes Yes Hardware NOP execution Hardware NOP execution Yes RAME = 1 PC (PC)+1 PC (PC)+1 Reset MCU Instruction execution MCU operation cycle Note: * Refer to figure 15, Flowchart for Exiting Low Power Modes, for IF and IM operation. Figure 20 MCU Operating (Low-Power Mode Operation) Notes: When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Edge detection is shown in figure 21. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. 39 HD404669 Series In figure 22(a), the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than interrupt frame. INT0 Sampling High Low Low Figure 21 Edge Detection INT0 INT0 Interrupt frame A: Low B: Low Interrupt frame A: High B: High (a) High level period (b) Low level period Figure 22 Sampling Example 40 HD404669 Series Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 23. As shown in table 13, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Set bits 0 and 1 (SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22, SSR23) of system clock select register 2 (SSR2: $02A) according to the frequency of the oscillator connected to OSC 1 and OSC2 (figures 24 and 25). The system clock division ratio can be set with bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2: $02A). The value set in these bits does not become valid until watch mode is entered. Therefore, the system clock must be halted temporarily when changing the division ratio. The system clock division ratio immediately after a reset or when stop mode is cleared can be selected by means of the SEL pin level, division-by-4 being selected when the SEL pin is at Vcc potential, and division-by-32 when at GND potential. Note: If the system clock select register 1 and 2 (SSR1, SSR2: $029, $02A) setting does not match the oscillator frequency, DTMF generation circuit and subsystems using the 32.768-kHz oscillation will malfunction. LSON OSC2 OSC1 System fOSC 1/4, 1/8, 1/16 or clock 1/32 oscillator division circuit fcyc tcyc Timing generation circuit oCPU System clock selection circuit oPER CPU with ROM, RAM, registers, flags, and I/O fX X1 X2 Subsystem clock oscillator fSUB 1/8 or 1/4 Timing division tsubcyc generation circuit circuit TMA3 bit Internal Peripheral module interrupts 1/8 division circuit fW tWcyc Timing generation circuit Time-base clock oCLK selection circuit Time base interrupt Figure 23 Clock Generation Circuit 41 HD404669 Series System clock select register 1 (SSR1: $029) Bit Initial value Read/Write Bit name SSR13 0 1 3 0 W SSR13 2 0 W SSR12 1 0 W SSR11 0 0 W SSR10 System clock SSR23 SSR22 SSR11 SSR10 selection 0 0 0 0 1 1 SSR12 0 1 32-kHz oscillation division ratio selection fSUB = fX/8 fSUB = fX/4 1 1 0 1 x 1 x 0 1 x 1 x 400 kHz 800 kHz 2 MHz 4 MHz 3.58 MHz 8 MHz 7.16 MHz 32-kHz oscillation stop Oscillation operates in stop mode Oscillation stops in stop mode Note: SSR13 is cleared only by a RESET input. SSR13 will not be cleared by a STOPC input during stop mode, and will retain its value. SSR13 will also not be cleared upon entering stop mode. Figure 24 System Clock Select Register 1 (SSR1) System clock select register 2 (SSR2: $02A) Bit Initial value Read/Write Bit name 3 0 W SSR23 2 0 W SSR22 1 0 W SSR21 0 0 W SSR20 System clock division ratio selection*1 Division by 4 Division by 8 Division by 16 Division by 32 SSR23 0 SSR22 0 1 System clock selection*2 Selected from 400 kHz, 800 kHz, 2 MHz, 4 MHz 3.58MHz 8MHz 7.16MHz SSR21 0 1 SSR20 0 1 0 1 1 0 1 Notes : *1 The DTMF generation circuit frequencies are not affected by the system clock division ratio setting. *2 See system clock select register 1 (SSR1). Figure 25 System Clock Select Register 2 (SSR2) 42 HD404669 Series Table 13 Oscillator Circuit Examples Circuit Configuration External clock operation External oscillator OSC 1 Circuit Constants -- Open OSC 2 Ceramic oscillator (OSC1, OSC 2) C1 OSC1 Ceramic oscillator Rf OSC2 C2 GND Ceramic oscillator: CSB400P22 (Murata) CSB400P (Murata) Rf = 1 M 20% C1 = C2 = 220 pF 5% Ceramic oscillator: CSB800J122 (Murata), CSB800J (Murata) Rf = 1 M 20% C1 = C2 = 220 pF 5% Ceramic oscillator: CSA2.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA3.58MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA8.00MT (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Crystal oscillator (OSC1, OSC 2) C1 Crystal oscillator Rf OSC1 Rf = 1 M 20% C1 = C2 = 10 to 22pF 20% Crystal oscillator: Equivalent circuit at left C0 =7pF max Rs = 100 max f = 400kHz, 800kHz, 2MHz, 3.58MHz, 4MHz, 7.16MHz, 8MHz OSC2 OSC2 C2 GND OSC1 L CS C0 RS 43 HD404669 Series Circuit Configuration Crystal oscillator (X1, X2) Crystal oscillator X2 C2 GND L X1 C0 CS RS X2 C1 X1 Circuit Constants Crystal oscillator: 32.768 kHz: MX38T (Nippon Denpa) C1 = C2 = 20 pF 20% RS=14 k C0=1.5 pF Notes: 1. Circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC1, OSC 2 (X1 and X2 pins), and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 26. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to VCC and leave the X2 pin open. GND X2 X1 RESET OSC2 OSC1 TEST GND Figure 26 Typical Layouts of Crystal and Ceramic Oscillator 44 HD404669 Series Input/Output The MCU has 47 input/output pins (D0 to D5, D 9 to D11, R00 to R43 and R60 to RA 1) and 5 input pins (D12, D13, RD0, RD1 and RE0). The features are described below. * Four pins D0 to D3 are high source current (10 mA maximum) input/output pins. * Five pins D 4, D5, and D9 to D11 are high sink current (15 mA maximum) input/output pins. * Certain of these input and output pins have shared functions with timers, the serial interface, and other peripheral functions. The D 12, D13, R0, R30, R32, R4, RD 0, RD1 and RE0 pins are shared function pins. The use of these pins as peripheral function pins takes precedence over their use as the D and R port pins. Pins that are set to function as peripheral function pins are switched automatically between their various functions and between the input and output directions according to their specifications under the peripheral function setting. * Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. * Peripheral function output pins are all CMOS outputs. However, the SO1 pin and the R43 port pin can be set to function as NMOS open drain outputs by software. * Since the MCU goes to the reset state internally after a reset and in stop mode, the peripheral function settings for these pins are cleared. Furthermore, since the data control registers (DCD and DCR) are also reset, the input/output pins go to the high-impedance state. * The D0 to D3 pin circuits include pull-down MOS transistors, and all the other pin circuits include pullup MOS transistors. Note that the on/off states of the pull-up and pull-down MOS transistors can be set independently of the setting for use as peripheral function pins. I/O buffer configurations are shown in figures 27 and 28, and I/O pin circuit structures are listed in tables 14 and 15. HLT VCC VCC Pull-up MOS Buffer control signal DCD,DCR Pull-up control signal MIS3 Output data PDR Input data Input control signal Figure 27 I/O Buffer Configuration (with Pull-Up MOS) 45 HD404669 Series Input control signal Input data VCC Buffer control signal DCD Pull-down MOS Output data PDR Pull-down MOS control signal MIS3 HLT Figure 28 I/O Buffer Configuration (with Pull-Down MOS) Table 14 I/O Pin Control by Register Settings (with Pull-Up MOS) MIS3 (bit 3 of MIS) DCD, DCR PDR CMOS buffer PMOS NMOS Pull-up MOS Note: 0 -- -- -- 0 1 -- -- -- 0 -- On -- 0 1 1 On -- -- 0 -- -- -- 0 1 -- -- On 0 -- On -- 1 1 1 On -- On 1. -- indicates off status. 2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions. Table 15 I/O Pin Control by Register Settings (with Pull-Down MOS) MIS3 (bit 3 of MIS) DCD PDR CMOS buffer PMOS NMOS Pull-down MOS Note: 0 -- -- -- 0 1 -- -- -- 0 -- On -- 0 1 1 On -- -- 0 -- -- On 0 1 -- -- -- 0 -- On On 1 1 1 On -- -- 1. -- indicates off status. 2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions. 46 HD404669 Series Table 16 Input/Output Pin Circuit Configurations I/O Pin Type Input/output pins VCC VCC Pull-up control signal Buffer control signal Circuit Configuration HLT MIS3 DCD,DCR Output data PDR Input data Input control signal Input control signal VCC Buffer control signal DCD Input data Relevant Pins D4 , D5 , D9 - D11 R0 0-R0 3 R1 0-R1 3 R2 0-R2 3 R3 0-R3 3 R4 0-R4 2 R6 0-R6 3 R7 0-R7 3 R8 0-R8 3 R9 0-R9 3 RA 0, RA 1 D0-D 3 Output data Pull-down control signal PDR MIS3 HLT HLT R4 3 VCC VCC Pull-up control signal Buffer control signal MIS3 DCR MIS2 PDR Output data Input data Input control signal Input pins Input data Input control signal D12, D13 RD0, RD1, RE 0 47 HD404669 Series Table 16 Input/Output Pin Circuit Configurations (cont) I/O Pin Type Peripheral function Input/output pins Circuit Configuration VCC Pull-up control signal HLT MIS3 Relevant Pins SCK 1 VCC Output data Input data SCK1 SCK1 Output pins VCC VCC Pull-up control signal HLT MIS3 SO1 PMOS control signal MIS2 Output data SO1 VCC VCC Pull-up control signal HLT MIS3 TOC, TOD Output data TOC,TOD HLT MIS3 PDR Input pins VCC SI 1, INT1, INT2, INT3, INT4, EVND Input data SI1,INT1,etc. INT0, STOPC, RESET Input data INT0, STOPC RESET Note: In a reset and in stop mode, since the I/O control registers are reset, input/output pins go to the highimpedance state and peripheral function selections are cleared. 48 HD404669 Series D Port The D port consists of 9 input/output pins and 2 input-only pins that can be addressed individually on a perbit basis. The D0 to D3 pins are high source current input/output pins and the D4, D 5, and D9 to D11 pins are high sink current input/output pins. The D 12 and D 13 pins are input-only pins. The D0 to D 5 and D9 to D11 pins can be set or reset by the SED/RED and SEDD/REDD instructions. The output data is stored in the port data register for the pin. All the D port pins can be tested using the TD and TDD instructions. The D port data control registers (DCD0 to DCD2: $02C to $02E) are used to turn the D0 to D5 and D9 to D11 pin output buffers on and off. The DCD registers are mapped to addresses in the RAM area. (figure 29.) The D12 and D 13 pins have shared functions as internal peripheral function pins and the STOPC and INT0 pins. Port mode register C (PMRC: $025) bits 2 and 3 (PMRC2 and PMRC3) are used to switch the functions of these pins. (figure 32.) 49 HD404669 Series Data control register DCD0 to DCD2 Bit Initial value Read/Write Bit name (DCD0 to 2: $02C to $02E) (DCR0 to 4, DCR6 to A: $030 to $034, $036 to $03A) 2 0 W 1 0 W 0 0 W 3 0 W DCD03, DCD02, DCD01- DCD00- DCD23 DCD22 DCD21 DCD10 DCR0 to DCR4 DCR6 to DCRA Bit Initial value Read/Write Bit name 3 0 W 2 0 W 1 0 W 0 0 W DCR03- DCR02- DCR01- DCR00- DCR43 DCR42 DCR41 DCR40 DCR63- DCR62- DCR61- DCR60- DCR93 DCR92 DCRA1 DCRA0 Note: Other bits are not used. All Bits CMOS Buffer Control 0 1 CMOS buffer Off (high-impedance) CMOS buffer active Correspondence between ports and DCD/DCR bits Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR6 DCR7 DCR8 DCR9 DCRA Bit 3 D3 -- D11 R03 R13 R23 R33 R43 R63 R73 R83 R93 -- Bit 2 D2 -- D10 R02 R12 R22 R32 R42 R62 R72 R82 R92 -- Bit 1 D1 D5 D9 R01 R11 R21 R31 R41 R61 R71 R81 R91 RA1 Bit 0 D0 D4 -- R00 R10 R20 R30 R40 R60 R70 R80 R90 RA0 Figure 29 Data Control Registers (DCD, DCR) 50 HD404669 Series R Port The R port consist of 38 input/output pins and 3 input pins that can be addressed in groups of 4 bits. Data can be input using the LAR and LBR instructions, and data can be output using the LRA and LRB instructions. Output data is stored in the port data register for the corresponding pin. The R port data control registers (DCR0 to DCR4 and DCR6 to DCRA: $030 to $034, and $036 to $03A) are used to turn the R port output buffers on and off. The DCR registers are mapped to addresses in the RAM area. (figure 29.) The R00 to R04 port pins have shared functions as the external interrupt input pins INT1 to INT4. Port mode register B (PMRB $024) is used to set these pins to their peripheral function usage. (figure 31.) The R40 port pin has a shared function as the EVND peripheral function pin. Port mode register C (PMRC: $025) bit 1 (PMRC1) is used to switch the function of this pin. (figure 32.) The R31 and R32 port pins have shared functions as the TOC and TOD peripheral function pins. Timer mode register C2 (TMC2: $014) bits 0 to 2 (TMC20 to TMC22) and timer mode register D2 (TMD2: $015) are used to set these pins to their peripheral function usage. (figures 33 and 34.) The R4 1 to R43 port pins have shared functions as the SCK 1, SI 1, and SO1 peripheral function pins. Serial mode register 1A (SM1A: $005) bit 3 (SM1A3) and port mode register A (PMRA: $004) bits 0 and 1 (PMRA0 and PMRA1) are used to set these pins to their peripheral function usage. (figures 30 and 35.) The R4 3/SO 1 pin can be set to function as an NMOS open drain output with the output buffer off. Miscellaneous register (MIS: $00C) bit 2 (MIS2) is used for this setting. (figure 37.) The RD0 and RD1 port pins have shared functions as the COMP 0 and COMP1 peripheral function pins. The compare enable register (CER: $018) is used to set these pins to their comparator pin functions. (figure 36.) Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name PMRA1 0 1 3 -- -- 2 -- -- 1 0 W 0 0 W Not used Not used PMRA1 PMRA0 R42/SI1 mode selection R42 SI1 PMRA0 0 1 R43/SO1 mode selection R43 SO1 Figure 30 Port Mode Register A (PMRA) 51 HD404669 Series Port mode register B (PMRB: $024) Bit Initial value Read/Write Bit name PMRB3 0 1 PMRB2 0 1 3 0 W PMRB3 2 0 W 1 0 W 0 0 W PMRB2 PMRB1 PMRB0 PMRB0 0 1 PMRB1 0 1 R00/INT1 mode selection R00 INT1 R01/INT2 mode selection R01 INT2 R03/INT4 mode selection R03 INT4 R02/INT3 mode selection R02 INT3 Figure 31 Port Mode Register B (PMRB) Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name PMRC3 0 1 PMRC2 0 1 3 0 W PMRC3 2 0 W PMRC2 1 0 W 0 -- -- PMRC1 Not Used D13/INT0 mode selection D13 INT0 D12/STOPC mode selection D12 STOPC PMRC1 0 1 R40/EVND mode selection R40 EVND Figure 32 Port Mode Register C (PMRC) 52 HD404669 Series Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name TMC22 0 3 -- -- 2 0 R/W 1 0 R/W TMC21 0 0 R/W TMC20 Not used TMC22 TMC21 0 TMC20 0 1 1 0 1 R31/TOC mode selection R31 TOC TOC TOC -- R31 port Toggle output 0 output 1 output Not Used 1 0 0 1 1 0 1 TOC PWM output Figure 33 Timer Mode Register C2 (TMC2) Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name TMD23 0 3 0 R/W TMD23 TMD22 0 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20 TMD21 0 TMD20 0 1 R32/TOD mode selection R32 TOD TOD TOD -- R32 port Toggle output 0 output 1 output Not used 1 0 1 1 0 0 1 1 0 1 TOD R32 PWM output Input capture (R32 port) 1 x x x x : Don't care Figure 34 Timer Mode Register D2 (TMD2) 53 HD404669 Series Serial mode register 1A (SM1A: $005) Bit Initial value Read/Write Bit name 3 0 W SM1A3 2 0 W SM1A2 1 0 W SM1A1 0 0 W SM1A0 Prescaler division ratio /2048 /512 /128 /32 /8 /2 -- -- SM1A3 0 1 R41/SCK1 mode selection R41 SCK1 SM1A2 0 SM1A1 0 SM1A0 0 1 SCK1 Output Output Output Output Output Output Output Input Clock source Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock 1 0 1 1 0 0 1 1 0 1 Figure 35 Serial Mode Register 1A (SM1A) Compare enable register (CER: $018) Bit Initial value Read/Write Bit name 3 0 W CER3 2 -- -- 1 0 W 0 0 W CER0 Not Used CER1 CER1 0 1 CER0 0 1 x Analog input pin selection COMP0 COMP1 Not Used x : Don't care CER3 Comparator operation selection 0 1 Normal operation (digital input mode): RD0/COMP0 and RD1/COMP1 pins function as R port pins Comparator operation (analog input mode): RD0/COMP0 and RD1/COMP1 pins function as comparator pins Figure 36 Compare Enable Register (CER) 54 HD404669 Series Pull-up and Pull-down MOS Transistor Control The D4, D5, D9 to D11, and the R port pins have built-in pull-up MOS transistors that can be controlled by software, and the D0 to D3 pins have built-in pull-down MOS transistors that can be controlled by software. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off control of that pin alone (tables 14, 15 and figure 37). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0 CMOS buffer on/off selection for pin R43/SO1 Active Off MIS3 0 1 Pull-up/Pull-down MOS transistor control Off Active MIS2 0 1 MIS1 MIS0 tRC selection. Refer to figure 18 in the operation modes section. Figure 37 Miscellaneous Register (MIS) How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k. Pins provided with pull-down MOS should be pulled down to GND potential with the built-in pull-down MOS or connected to GND. 55 HD404669 Series Prescalers The MCU has the following two prescalers, S and W. The prescalers operating conditions are listed in table 17, and the prescalers output supply is shown in figure 38. The timers A, C, D input clocks except external events, the serial transmit clock except the external clock, are selected from the prescaler outputs, depending on corresponding mode registers. Table 17 Prescaler Operating Conditions Prescaler Prescaler S Input Clock System clock (in active and standby mode), Subsystem clock (in subactive mode) Clock derived by dividing subsystem clock 32.768 kHz oscillation by 8 Reset Conditions MCU reset Stop Conditions MCU reset, stop mode, watch mode MCU reset, stop mode Prescaler W MCU reset, software* Note: * If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00. Subsystem clock Prescaler W Timer A Timer C Timer D System clock Clock selector Prescaler S Serial interface 1 Figure 38 Prescaler Output Supply Prescaler Operation Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. 56 HD404669 Series Timers The MCU has three timer/counters (A, C, D). * Timer A: Free-running timer * Timer C: Multifunction timer * Timer D: Multifunction timer Timer A is an 8-bit free-running timer. Timers C, D are 8-bit multifunction timers, whose functions are listed in table 18. The operating modes are selected by software. Table 18 Timer Functions Functions Clock source Prescaler S Prescaler W External event Timer functions Free-running Time-base Event counter Reload Watchdog Input capture Timer outputs Toggle 0 output 1 output PWM Note: -- implies not available. Timer A Available Available -- Available Available -- -- -- -- -- -- -- -- Timer C Available -- -- Available -- -- Available Available -- Available Available Available Available Timer D Available -- Available Available -- Available Available -- Available Available Available Available Available Timer A Timer A Functions: Timer A has the following functions. * Free-running timer * Clock time-base The block diagram of timer A is shown in figure 39. 57 HD404669 Series 32.768-kHz oscillator 1/4 1/2 2 fW 1/2 twcyc Selector Internal data bus Selector Clock Timer counter A (TCA) Overflow fW twcyc Prescaler W (PSW) /2 /8 / 16 / 32 Timer A interrupt request flag (IFTA) Selector /2 /4 /8 / 32 / 128 / 512 / 1024 / 2048 System clock Data bus o PER Prescaler S (PSS) 3 Timer mode register A (TMA) Clock line Signal line Figure 39 Block Diagram of Timer A Timer A Operations Free-running timer operation: The timer A input clock is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $001, 2). Timer A continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. Realtime clock time base operation: Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1. As the prescaler W output is input to timer counter A (TCA), interrupts are generated with accurate timing using the 32.768 kHz crystal oscillator as the basic clock.When timer A is used as the realtime clock time base, prescaler W and timer counter A (TCA) can be reset to $00 by the program. Registers for Timer A Operation Timer A operating modes are set by the following registers. Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 40. 58 HD404669 Series Timer mode register A (TMA: $008) Bit Initial value Read/Write Bit name 3 0 W TMA3 2 0 W TMA2 1 0 W TMA1 0 0 W TMA0 Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 x : Don't care x PSS PSS PSS PSS PSS PSS PSS PSS PSW PSW PSW PSW -- -- -- 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc 32tWcyc 16tWcyc 8tWcyc 2tWcyc 1/2tWcyc Not used Reset PSW and TCA Operating mode Timer A mode Time-base mode Note: 1. tWcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 40 Timer Mode Register A (TMA) 59 HD404669 Series Timer C Timer C Functions: Timer C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 41. 60 HD404669 Series System reset signal Watchdog on flag (WDON) TOC Timer output control logic Watchdog timer control logic Timer C interrupt request flag (IFTC) System clock o PER Timer read register CL (TRCL) /2 Prescaler S (PSS) /4 /8 / 32 / 128 / 512 / 1024 / 2048 Selector clock Free-running/reload control 4 Timer read register CU (TRCU) Timer counter C (TCCL) 4 (TCCU) 4 Overflow Timer write register C (TWCL) (TWCU) 3 Timer mode register C1 (TMC1) 3 Timer output control Data bus Clock line Signal line Timer mode register C2 (TMC2) Figure 41 Block Diagram of Timer C Internal data bus 61 HD404669 Series Timer C Operations Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C (TWCL: $00E, TWCU: $00F); if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2 ). The timer C interrupt request flag is reset by the program, an MCU reset or a transition to stop mode. For details, see figure 3, Configuration of Interrupt Control Bits and Register Flag Area, and table 1, Initial Values after MCU Reset. Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). With timer C, the R3 1/TOC pin is designated as the TOC pin, and toggle waveform output, low-level output, high-level output, or PWM waveform output can be selected, by timer mode register C2 (TMC2: $014). TOC pin output is initialized to the low level by an MCU reset. * Toggle output With toggle output, the output level is changed upon input of the next clock pulse after the timer C value reaches $FF. Use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. The output waveform is shown in figure 42. * Low-level output With low-level output, the output is changed to the low level when timer C overflows. This function should be used when the output is high. * High-level output With high-level output, the output is changed to the high level when timer C overflows. This function should be used when the output is low. * PWM output With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 42, according to the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). 62 HD404669 Series Toggle output waveform (timers C and D) Free-running timer 256 clock cycles Reload timer 256 clock cycles (256 - N) clock cycles (256 - N) clock cycles PWM output waveform (timers C and D) T x (N + 1) TMC13 = 0 TMD13 = 0 (free-running timer) T TMC13 = 1 TMD13 = 1 (reload timer) T x (256 - N) Notes: T: Counter input clock period The clock input source and division ratio are controlled by timer mode register C1 and timer mode register D1. N: Value in timer write register C or timer write register D (When N = 255 (= $FF), PWM output is always fixed low.) T x 256 Figure 42 Timer Output Waveforms 63 HD404669 Series Registers for Timer C Operation By using the following registers, timer C operation modes are selected and the timer C count is read and written. * * * * Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload timer function, and the prescaler division ratio as shown in figure 43. It is reset to $0 by MCU reset or in stop mode. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Timer mode register C1 (TMC1: $00D) Bit Initial value Read/Write Bit name TMC13 0 1 3 0 W TMC13 2 0 W TMC12 1 0 W TMC11 0 0 W TMC10 TMC12 0 TMC11 0 TMC10 0 1 1 0 1 1 0 0 1 1 0 1 Input clock period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc Free-running/reload timer selection Free-running timer Reload timer Figure 43 Timer Mode Register C1 (TMC1) 64 HD404669 Series Timer mode register C2 (TMC2: $014): Timer mode register C2 (TMC2: $014) is a 3-bit read/write register, used to switch the function of the R31/TOC pin and select the timer C output mode as shown in figure 44. Timer mode register C2 (TMC2: $014) is reset to $0 by an MCU reset or in stop mode. Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- 2 0 R/W 1 0 R/W TMC21 0 0 R/W TMC20 Not used TMC22 TMC22 0 TMC21 0 TMC20 0 1 R31/TOC mode selection R31 TOC TOC TOC -- R31 port Toggle output 0 output 1 output Not used 1 0 1 1 0 0 1 1 0 1 TOC PWM output Figure 44 Timer Mode Register C2 (TMC2) Timer write register C (TWCL: $00E, TWCU: $00F): Timer write register C (TWCL: $00E, TWCU: $00F) is a write-only register composed of a lower digit (TWCL: $00E) and an upper digit (TWCU: $00F). The lower digit (TWCL) of timer write register C is reset to $0 by an MCU reset or in stop mode, while the upper digit (TWCU) is undetermined. Timer C can be initialized by writing to timer write register C (TWCL, TWCU). To write the data, first write the lower digit (TWCL). The lower digit write does not change the timer C value. Next, write the upper digit (TWCU). Timer C is then initialized to the timer write register C (TWCL, TWCU) value. When writing to timer write register C (TWCL, TWCU) from the second time onward, if it is not necessary to change the lower digit (TWCL) reload value, timer C initialization is completed by the upper digit write alone. 65 HD404669 Series Timer write register C (lower digit) (TWCL: $00E) Bit Initial value Read/Write Bit name 3 0 W TWCL3 2 0 W TWCL2 1 0 W TWCL1 0 0 W TWCL0 Figure 45 Timer Write Register C Lower Digit (TWCL) Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W TWCU3 W TWCU2 W TWCU1 W TWCU0 Figure 46 Timer Write Register C Upper Digit (TWCU) Timer read register C (TRCL: $00E, TRCU: $00F): Timer read register C (TRCL: $00E, TRCU: $00F) is a read-only register composed of a lower digit (TRCL: $00E), and an upper digit (TRCU: $00F) from which the value of the upper digit of timer C is read directly. First, read the upper digit (TRCU) of timer read register C. The current value of the timer C upper digit is read and, at the same time, the value of the timer C lower digit is latched in the lower digit (TRCL) of timer read register C. The timer C value is obtained when the upper digit (TRCU) of timer read register C is read by reading the lower digit (TRCL) of timer read register C. Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R TRCL3 R TRCL2 R TRCL1 R TRCL0 Figure 47 Timer Read Register C Lower Digit (TRCL) 66 HD404669 Series Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R TRCU3 R TRCU2 R TRCU1 R TRCU0 Figure 48 Timer Read Register C Upper Digit (TRCU) Timer D Timer D Functions: Timer D has the following functions. * * * * Free-running/reload timer External event counter Timer output operation (toggle, low-level, high-level, and PWM outputs) Input capture timer The block diagram for each operation mode of timer D is shown in figures 49(1) and 49(2). 67 HD404669 Series Timer D interrupt request flag (IFTD) Edge detection logic Timer read register DU (TRDU) Timer read register DL (TRDL) /2 Prescaler S (PSS) /4 / 32 / 128 / 512 / 2048 Selector /8 clock Free-running/reload control Timer counter D (TCDL) 4 Timer write register D (TWDL) (TWDU) (TCDU) 4 4 Overflow EVND System clock oPER 3 Timer mode register D1 (TMD1) 2 Edge detection select register 2 Edge detection control (ESR2) Timer mode register D2 (TMD2) Timer output control logic TOD Data bus Clock line Signal line Figure 49(1) Block Diagram of Timer D (Free-Running/Reload Timer/Event Counter Modes) 68 Internal data bus HD404669 Series Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD) Error control logic EVND Edge detection logic Read signal System clock o PER Timer read register D (TRDL) /2 Prescaler S (PSS) /4 / 32 / 128 / 512 / 2048 Selector /8 clock Timer counter D (TCDL) (TCDU) 4 (TRDU) 4 Internal data bus Overflow Input capture timer control 3 Timer mode register D1 (TMD1) 2 Timer mode register D2 (TMD2) Edge detection select register 2 Edge detection control (ESR2) Data bus Clock line Signal line Figure 49(2) Block Diagram of Timer D (Input Capture Timer) 69 HD404669 Series Timer D Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D (TWDL: $011, TWDU: $012); if the freerunning timer function is enabled, the timer is initialized to $00 and then incremented again. The timer D interrupt request flag (IFTD: $003, 0) is reset by the program, and by an MCU reset or a transition to stop mode. For details, see figure 3, Configuration of Interrupt Control Bits and Register Flag Areas, and table 1, Initial Values after MCU Reset. * External event counter operation: When external event input is designated for the input clock by timer mode register D1 (TMD1), timer D operates as an external event counter.In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. * Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle Low-level output Hige-level output PWM output Pin R3 2/TOD is set to TOD. Toggle output: The operation is basically the same as that of timer-C's toggle output. 0 output: The operation is basically the same as that of timer-C's 0 output. 1 output: The operation is basically the same as that of timer-C's 1 output. PWM output: The operation is basically the same as that of timer-C's PWM output. 70 HD404669 Series * Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 0) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00. Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 50. Timer mode register D1 (TMD1: $010) is reset to $0 by an MCU reset or in stop mode. * Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. * When selecting the input capture timer operation, select the internal clock as the input clock source. When designating external event input for the input clock, set bit 1 (PMRC1) of port mode register C (PMRC) to 1. 71 HD404669 Series Timer mode register D1 (TMD1: $010) Bit Initial value Read/Write Bit name 3 0 W TMD13 2 0 W TMD12 1 0 W TMD11 0 0 W TMD10 Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc EVND (external event input) TMD13 0 1 Free-running/reload timer selection Free-running timer Reload timer TMD12 0 TMD11 0 TMD10 0 1 1 0 1 1 0 0 1 1 0 1 Figure 50 Timer Mode Register D1 (TMD1) 72 HD404669 Series Timer mode register D2 (TMD2: $015): Timer mode register D2 (TMD2: $015) is a 4-bit read/write register, used to switch the function of the R32/TOD pin and select the timer D output mode as shown in figure 51. Timer mode register D2 (TMD2: $015) is reset to $0 by an MCU reset and in stop mode. Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20 TMD23 0 TMD22 0 TMD21 0 TMD20 0 1 R32/TOD mode selection R32 TOD TOD TOD -- R32 port Toggle output 0 output 1 output Not used 1 0 1 1 0 0 1 1 0 1 TOD R32 PWM output Input capture (R32 port) 1 x x x x : Don't care Figure 51 Timer Mode Register D2 (TMD2) Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of the lower digit (TWDL: $011) and the upper digit (TWDU: $012). The operation of timer write register D is basically the same as that of timer write register C (TWCL: $00E, TWCU: $00F). Timer write register D (lower digit) (TWDL: $011) Bit Initial value Read/Write Bit name 3 0 W TWDL3 2 0 W TWDL2 1 0 W TWDL1 0 0 W TWDL0 Figure 52 Timer Write Register D Lower Digit (TWDL) 73 HD404669 Series Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W TWDU3 W TWDU2 W TWDU1 W TWDU0 Figure 53 Timer Write Register D Upper Digit (TWDU) Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of the lower digit (TRDL) and the upper digit (TRDU). The operation of timer read register D is basically the same as that of timer read registerC (TRCL: $00E, TRCU: $00F). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R TRDL3 R TRDL2 R TRDL1 R TRDL0 Figure 54 Timer Read Register D Lower Digit (TRDL) Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R TRDU3 R TRDU2 R TRDU1 R TRDU0 Figure 55 Timer Read Register D Upper Digit (TRDU) 74 HD404669 Series Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown in figure 56. It is reset to $0 by MCU reset. Port mode register C (PMRC: $025) bits 3 and 1 (PMRC3, PMRC1) are reset to 00 by an MCU reset or in stop mode. Bit 2 (PMRC2) is reset to 0 by an MCU reset, but retains its previous setting in stop mode. Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name PMRC2 0 1 PMRC3 0 1 3 0 W PMRC3 2 0 W 1 0 W 0 -- -- PMRC2 PMRC1 Not Used PMRC1 0 1 R40/EVND pin mode selection R40 EVND D12/STOPC pin mode selection D12 STOPC D13/INT0 pin mode selection D13 INT0 Figure 56 Port Mode Register C (PMRC) 75 HD404669 Series Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 57. It is reset to $0 by an MCU reset or in stop mode. Detection edge select register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W ESR22 1 0 W ESR21 0 0 W ESR20 ESR23 0 ESR22 0 1 EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection* ESR21 0 ESR20 0 1 INT4 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection* 1 0 1 1 0 1 Note: * Both falling and rising edges are detected. Figure 57 Detection Edge Select Register 2 (ESR2) 76 HD404669 Series Serial Interface Serial Interface Overview Function * 8-bit serial data transmission/reception Features * Multiple transmit clock sources External clock Internal prescaler output clock System clock * High/low control in idle states Configuration * * * * * * * Serial data register 1 (SR1L: $006, SR1U: $007) Serial mode register 1 A (SM1A: $005) Serial mode register 1 B (SM1B: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC1) Selector The block diagram of the serial interface is shown in figure 58. 77 HD404669 Series Octal counter (OC1) Serial 1 interrupt request flag (IFS1) SO1 Idle control logic SCK1 I/O control logic Clock Serial data register 1 (SR1L, SR1U) Internal data bus SI1 Transfer control Serial mode register 1A (SM1A) Serial mode register 1B (SM1B) 1/2 Prescaler S (PSS) /2 /8 /32 /128 /512 /2048 1/2 Selector Data bus Clock line Signal line Figure 58 Block Diagram of Serial Interface 78 Selector System clock o PER HD404669 Series Serial Interface Operation Selecting and Changing the Operating Mode: Table 19 lists the serial interface's operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial mode register 1A (SM1A: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to serial mode register 1A (SM1A: $005). Note that the serial interface is initialized by writing data to serial mode register 1A(SM1A: $005). Refer to the following Serial Mode Register 1A section for details. Pin Setting: The R41/SCK 1 pin is controlled by writing data to serial mode register 1A (SM1A: $005). The R42/SI 1 and R43/SO 1 pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the following Registers for Serial Interface section for details. Transmit Clock Source Setting: The transmit clock source is set by writing data to serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following Registers for Serial Interface section for details. Data Setting: Transmit data is set by writing data to the serial data register 1 (SR1L: $006, SR1U: $007). Receive data is obtained by reading the contents of the serial data register 1 (SR1L: $006, SR1U: $007). The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO1 pin is invalid until the first data is output after MCU reset, or until the High/Low level control in idle states is performed. Table 19 Serial Interface Operating Modes SM1A Bit 3 1 PMRA Bit 1 0 Bit 0 0 1 1 0 1 Operating Mode Serial clock continuous output mode Transmit mode Receive mode Transmit/receive mode Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and the transfer stops. When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 2 to 0 (SM1A2- SM1A0) of serial mode register 1A (SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 20. 79 HD404669 Series Table 20 Serial Transmit Clock (Prescaler Output) SM1B Bit 0 0 Bit 2 0 SM1A Bit 1 0 Bit 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 Transmit Clock Division Ratio (oPER / 2048) / 2 (oPER / 512) / 2 (oPER / 128) / 2 (oPER / 32) / 2 (oPER / 8) / 2 (oPER / 2) / 2 (oPER / 2048) / 4 (oPER / 512) / 4 (oPER / 128) / 4 (oPER / 32) / 4 (oPER / 8) / 4 (oPER / 2) / 4 Transmit Clock Frequency 4096t cyc 1024t cyc 256t cyc 64t cyc 16t cyc 4t cyc 8192t cyc 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc Operating States: The serial interface has the operating states shown in figure 59 in external clock mode and internal clock mode. STS wait state Transmit clock wait state Transfer state Serial clock continuous output state (internal clock mode only) * STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), the serial interface enters transmit clock wait state. 80 HD404669 Series External clock mode STS wait state (Octal counter 1 = 000, transmit clock disabled) 00 MCU reset SM1A write 04 01 STS instruction 02 Transmit clock 06 SM1A write (IFS1 1) Transmit clock wait state (Octal counter 1 = 000) Transfer state (Octal counter 1 = 000) 03 8 transmit clocks 05 STS instruction (IFS1 1) Internal clock mode STS wait state (Octal counter 1 = 000, transmit clock disabled) SM1A write 18 Continuous clock output state (PMRA 0, 1 = 00) 10 MCU reset 13 SM1A write 14 11 STS instruction 8 transmit clocks 16 SM1A write (IFS1 1) Transmit clock 17 12 Transmit clock Transmit clock wait state (Octal counter 1 = 000) 15 STS instruction (IFS1 1) Transfer state (Octal counter 1 = 000) Note: Refer to the Operating States section for the corresponding encircled numbers. Figure 59 Serial Interface State Transitions * Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04, 14) in transmit clock wait state. * Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes the serial interface, and STS wait state is entered. 81 HD404669 Series If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK 1 pin. When bits 1 and 0 (PMRA1, PMRA0) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait state is entered. High/Low Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state, the output level of the SO 1 pin can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1. The high/low control example is shown in figure 60. Note that the high/low level cannot be controlled in transfer state. 82 , Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SM1A write SM1B write External clock selection Output level control in idle states Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin Undefined Idle LSB IFS1 External clock mode Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SM1A write SM1B write Internal clock selection Output level control in idle states Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (output) SO1 pin Undefined Idle LSB IFS1 Internal clock mode HD404669 Series Transmit clock wait state STS wait state Dummy write for state transition Output level control in idle states MSB Idle Flag reset at transfer completion STS wait state Output level control in idle states MSB Idle Flag reset at transfer completion Figure 60 Example of Serial Interface Operation Sequence 83 HD404669 Series Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 61. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial 1 interrupt request flag is reset, and a dummy write is performed to serial mode register 1A (SM1A: $005). The serial interface then returns to the STS wait state, and the serial 1 interrupt request flag (IFS1: $003, 2) is set again. It is therefore possible to detect a serial clock error by testing the serial 1 interrupt request flag after the dummy write to serial mode register 1A. 84 Transmit clock wait state State SCK1 pin (input) SM1A write IFS1 Transfer completion (IFS1 1) Interrupts inhibited IFS1 0 SM1A write IFS1 = 1? Yes Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transfer state Noise 1 2 3 4 5 6 Flag set because octal counter reaches 000 Transmit clock error detection procedure HD404669 Series Transmit clock wait state Transfer state 7 8 Transfer state has been entered by the transmit clock error. When SM1A is written, IFS1 is set. Flag reset at transfer completion Figure 61 Transmit Clock Error Detection 85 HD404669 Series Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1A (SM1A: $005) again. * Serial 1 interrupt request flag (IFS1: $003, bit 2) set: If the state is changed from transfer to another by writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag 1 (IFS1: $003, 2) is not set. To set the serial interrupt request flag, serial mode register 1A (SM1A: $005) write or STS instruction execution must be programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing the input instruction to port R4. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial Mode Register 1A (SM1A: $005) Serial Mode Register 1B (SM1B: $028) Serial Data Register 1 (SR1L: $006, SR1U: $007) Port Mode Register A (PMRA: $004) Miscellaneous Register (MIS: $00C) Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 62). * * * * R4 1/SCK 1 pin function selection Transfer clock selection Prescaler division ratio selection Serial interface initialization Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by an MCU reset or when the MCU switches to stop mode. A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock to the serial data register 1 (SR1L: $006, SR1U: $007) and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that. 86 HD404669 Series Serial mode register 1A (SM1A: $005) Bit Initial value Read/Write Bit name 3 0 W SM1A3 2 0 W SM1A2 1 0 W SM1A1 0 0 W SM1A0 Prescaler Clock source division ratio Prescaler Refer to table 20 SM1A3 0 1 R41/SCK1 mode selection R41 SCK 1 SM1A2 0 SM1A1 0 SM1A0 0 1 SCK 1 Output 1 0 1 1 0 0 1 1 0 1 Output Input System clock External clock -- -- Figure 62 Serial Mode Register 1A (SM1A) Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 63). * Serial clock division ratio selection * High/low level control in idle states Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data transfer. Setting bit 0 (SM1B0) of the serial mode register 1B (SM1B: $028) selects the divisor applied to the prescaler output used for the transfer clock. Only bit 0 (SM1B0) is cleared to 0 by an MCU reset or when the MCU switches to stop mode. Bit 1 (SM1B1) of the serial mode register (SM1B: $028) controls the high/low state of the SO1 pin during idle. The SO 1 pin changes state as soon as the high/low control bit is written. The value of this bit is undefined after a reset or when the MCU enters stop mode. 87 HD404669 Series Serial mode register 1B (SM1B: $028) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 Undefined W 0 0 W SM1B0 Not used Not used SM1B1 SM1B1 0 1 Output level control in idle states Low level High level SM1B0 0 1 Transmit clock division ratio Prescaler output divided by 2 Prescaler output divided by 4 Figure 63 Serial Mode Register 1B (SM1B) Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 64 and 65). * Transmission data write and shift * Receive data shift and read Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock. Input/output timing is shown in figure 66. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register 1 (lower digit) (SR1L: $006) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R/W SR1L3 R/W SR1L2 R/W SR1L1 R/W SR1L0 Figure 64 Serial Data Register 1 (SR1L) Serial data register 1 (upper digit) (SR1U: $007) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R/W SR1U3 R/W SR1U2 R/W SR1U1 R/W SR1U0 Figure 65 Serial Data Register 1 (SR1U) 88 HD404669 Series Transmit clock 1 Serial output data LSB MSB 2 3 4 5 6 7 8 Serial input data latch timing Figure 66 Serial Interface Output Timing Port Mode Register A (PMRA: $004): This register has the following functions (figure 67). * R4 2/SI 1 pin function selection * R4 3/SO 1 pin function selection Port mode register A (PMRA: $004) is a 2-bit write-only register. It is reset to "--00" by an MCU reset or when the MCU switches to stop mode. Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 W 0 0 W Not used Not used PMRA1 PMRA0 PMRA1 0 1 R42/SI1 mode selection R42 SI1 PMRA0 0 1 R43/SO1 mode selection R43 SO1 Figure 67 Port Mode Register A (PMRA) 89 HD404669 Series Miscellaneous Register (MIS: $00C): This register has the following function (figure 68). * R4 3/SO 1 pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by an MCU reset or in stop mode. Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0 MIS3 0 1 MIS2 0 1 Pull-up/Pull-down MOS control Off On MIS1 0 MIS0 0 tRC 0.12207 ms 0.24414 ms* 1 R43/SO1 PMOS control On 1 Off 1 0 7.8125 ms 31.25 ms Not used Note: * The value is applied only when direct transfer operation is used. Figure 68 Miscellaneous Register (MIS) 90 HD404669 Series DTMF Generation Circuit The MCU provides a dual-tone multifrequency (DTMF) generation circuit. Figure 69 shows a block diagram of the DTMF circuit. A DTMF signal consists of two sine waves corresponding to the numbers and symbols on a telephone keypad. DTMF signals are used to access telephone switching equipment. Figure 70 shows the DTMF frequency matrix. The OSC clock (400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz, or 8 MHz) is changed into seven clock signals through the division circuit (1/2, 1/5, 1/9*, 1/10, 1/18*, and 1/20). The DTMF circuit uses one of the seven clock signals, which is selected by the system clock select register 1, 2 (SSR1: $029, SSR2: $02A) depending on the OSC clock frequency. The DTMF circuit has transformed programmable dividers, sine wave counters, and control registers. The DTMF generation circuit is controlled by the following three registers. 91 HD404669 Series TONER Sine wave counter D/A Feedback VTref TONER output control Transformation program divider 2 Tone generator mode register (TGM) TONEC Feedback 2 Tone generator control register (TGC) TONEC output control fOSC 1/2 1/5 1/9* 1/10 1/18* 1/20 2 Selector 400 kHz* 2 System clock select register 1 (SSR1) System clock select register 2 (SSR2) Data bus Clock line Signal line Note: * 397.8 kHz when an fOSC frequency of 3.58 MHz or 7.16 MHz is used. Figure 69 Block Diagram of DTMF Circuit 92 Internal data bus Sine wave counter D/A Transformation program divider HD404669 Series 1 2 3 A R1 (697Hz) 4 5 6 B R2 (770Hz) 7 8 9 C R3 (852Hz) 0 # D R4 (941Hz) C1 (1,209Hz) C2 (1,336Hz) C3 (1,477Hz) Figure 70 DTMF Keypad and Frequencies Tone Generator Mode Register (TGM: $019): The tone generator mode register (TGM: $019) is a 4-bit write-only register that controls the generated DTMF frequencies as shown in figure 71. TGM is initialized to $0 by an MCU reset or in stop mode, watch mode, and subactive mode. Tone generator mode register (TGM: $019) Bit Initial value Read/Write Bit name 3 0 W TGM3 2 0 W TGM2 1 0 W TGM1 0 0 W TGM0 C4 (1,633Hz) TGM3 0 0 1 1 TGM2 0 1 0 1 TONEC output frequencies C1 (1,209 Hz) C2 (1,336 Hz) C3 (1,477 Hz) C4 (1,633 Hz) TGM1 0 0 1 1 TGM0 0 1 0 1 TONER output frequencies R1 (697 Hz) R2 (770 Hz) R3 (852 Hz) R4 (941 Hz) Figure 71 Tone Generator Mode Register (TGM) 93 HD404669 Series Tone Generator Control Register (TGC: $01A): The tone generator control register (TGC: $01A) is a 3bit write-only register that controls starting and stopping of DTMF signal generation as shown in figure 72. TGC is initialized to 000- by an MCU reset or in stop mode, watch mode, or subactive mode. TONEC output and TONER output are controlled individually by TGC3 and TGC2, and overall DTMF control is performed by TGC1. Tone generator control register (TGC: $01A) Bit Initial value Read/Write Bit name TGC3 0 1 TGC2 0 1 3 0 W TGC3 2 0 W TGC2 1 0 W TGC1 0 -- -- Not used TGC1 0 1 DTMF enable bit DTMF disable DTMF enable TONEC output control (column) No output TONEC output (active) TONER output control (row) No output TONER output (active) Figure 72 Tone Generator Control Register (TGC) System Clock Select Registers 1 and 2 (SSR1: $029 and SSR2: $02A): The system clock select registers 1 and 2 (SSR1: $029 and SSR2: $02A) are 4-bit write-only registers. Applications must set these registers to the values shown in figure 73 that correspond to the frequency of the oscillator circuit connected to the OSC1 and OSC2 pins. If the oscillator frequency and the system clock select register settings differ from the combination shown in figure 73, the DTMF output frequencies will not have the correct values as shown in figure 71. Except for the SSR13 bit, the system clock select registers 1 and 2 (SSR1: $029 and SSR2: $02A) are initialized to $0 by an MCU reset or when the MCU switches to stop mode. 94 HD404669 Series System clock select register 1 (SSR1: $029) Bit Initial value Read/Write Bit name 3 0 W SSR13*1 2 0 W SSR12 1 0 W SSR11 0 0 W SSR10 SSR12 0 1 SSR13 0 1 32 kHz division ratio switch fSUB=fX/8 fSUB=fX/4 SSR23 SSR22 SSR11 SSR10 System clock selection 0 0 0 1 0 1 0 1 1 1 0 x 1 x x 1 x 400kHz 800 kHz 2 MHz 4 MHz 3.58 MHz 8 MHz 7.16 MHz x : Don't care 32 kHz oscillation stop setting Oscillation continues in stop mode Oscillation stops in stop mode 1 System clock select register 2 (SSR2: $02A) Bit Initial value Read/Write Bit name SSR21 0 1 3 0 W SSR23 SSR20 0 1 0 1 2 0 W SSR22 1 0 W SSR21 0 0 W SSR20 System clock division ratio selection*2 Division by 4 Division by 8 Division by 16 Division by 32 Notes: 1. SSR13 is cleared to 0 only by RESET input. In the case of STOPC input in stop mode it retains its current value. SSR13 is not reset in stop mode 2. The DTMF generation circuit frequencies are not affected by the system clock division ratio setting. Figure 73 System Clock Select Register 1 and 2 (SSR1, SSR2) 95 HD404669 Series DTMF Output: The sine waves of the row-group and column-group are output from the DTMF output pins (TONER and TONEC). These are output by a high-precision resistance-ladder type D/A converter. Figure 74 shows the TONE output pin equivalent circuit, and figure 75 shows the output waveform. One output waveform cycle is composed of 32 slots, giving stable output with a low distortion factor. Table 21 shows the deviation of the output frequencies with respect to the standard DTMF signals. Table 21 Frequency Deviation of the MCU from Standard DTMF (fOSC=400kHz, 800kHz, 2MHz, 4MHz, 8MHz ) Standard DTMF (Hz) R1 R2 R3 R4 C1 C2 C3 C4 697 770 852 941 1,209 1,336 1,477 1,633 MCU (Hz) 694.44 769.23 851.06 938.97 1,212.12 1,333.33 1,481.48 1,639.34 Deviation from Standard (%) -0.37 -0.10 -0.11 -0.22 0.26 -0.20 0.30 0.39 Table 22 Frequency Deviation of the MCU from Standard DTMF (fOSC=3.58kHz, 7.16MHz ) Standard DTMF (Hz) R1 R2 R3 R4 C1 C2 C3 C4 697 770 852 941 1,209 1,336 1,477 1,633 MCU (Hz) 690.58 764.96 846.33 933.75 1,205.39 1,325.92 1,473.25 1,630.23 Deviation from Standard (%) -0.92 -0.65 -0.67 -0.77 -0.30 -0.75 -0.25 -0.17 Notes: 1. The DTMF signal frequency deviation must be within 1.5%, totaling the values in tables 21 and 22 and the precision of the oscillator used. When an f OSC frequency of 3.58 MHz or 7.16 MHz is used, in particular, the frequency deviation is greater (max - 0.92%) than with an fOSC frequency of 400 kHz, 800 kHz, 2 MHz, 4 MHz, or 8 MHz, and thorough consultation with the oscillator manufacturer is essential before deciding on the oscillator to be used. 2. This frequency deviation does not include the frequency deviation of the oscillator. Also, the ratio of oscillator waveform high-level width and low-level width in this case is 50% : 50%. 96 HD404669 Series Switch control VTref GND TONER TONEC Figure 74 Tone Output Equivalent Circuit VTref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND Time slots Figure 75 Waveform of Tone Output 97 HD404669 Series Comparator The MCU has a built-in comparator that compare an input voltage with the reference voltage (VCref ). The comparator block diagram is shown in figure 76. The comparator can operate in active mode and subactive mode. They are halted in other modes. Selector COMP0 COMP1 VCref + Comparator Compare data register (CDR) Internal data bus - 2 Compare enable register (CER) Figure 76 Comparator Block Diagram Comparator Operation (1) Analog input pin selection is performed by bits 0 and 1 (CER0, CER1) of the compare enable register (CER). Setting bit 3 (CER3) to 1 places the RD0/COMP0 and RD1/COMP1 pins in analog input mode and starts comparator operation. While comparator operation is in progress, none of these pins (including pins not used for comparison) can be used as R port pins. (2) The compare result can be read by means of a bit test instruction (TM or TMD) on the compare data register (CDR) bit corresponding to the selected analog input pin. 98 HD404669 Series Registers Used by Comparator * Compare enable register (CER: $018) * Compare data register (CDR: $017) Compare enable register (CER: $018): The compare enable register (CER) is a 3-bit write-only register that selects comparator operation and the analog input pin (figure 77). CER is reset by an MCU reset or in stop mode. Compare enable register (CER: $018) Bit Initial value Read/Write Bit name CER1 0 1 CER3 0 3 0 W CER3 CER0 0 1 2 -- -- 1 0 W 0 0 W CER0 Not Used CER1 Analog input pin selection COMP0 COMP1 Not Used x Comparator operation selection Comparator operation not selected: Digital input mode RD0/COMP0 and RD1/COMP1 pins function as R port pins Comparator operation selected: Analog input mode RD0/COMP0 and RD1/COMP1 pins function as comparator pins 1 x : Don't care Figure 77 Compare Enable Register (CER) Compare data register (CDR: $017): The compare data register (CDR) is a 2-bit read-only register that holds the result of the comparison between the analog input pin and the reference voltage (figure 78). When comparator operation is started (CER3 is set to 1), the result of the comparison between the analog input pin selected by the compare enable register (CER) and the reference voltage is read into the corresponding bit of the compare data register (CDR). The value of the other bits in CDR is undetermined. The CDR value is not retained after the comparator operation (when CER3 = 0), and is undetermined except during comparator operation. 99 HD404669 Series Compare data register (CDR: $017) Bit Initial value Read/Write Bit name CDR 0 0 1 3 -- -- 2 -- -- 1 R 0 R CDR0 Undetermined Undetermined Not Used Not Used CDR1 Result of comparison between COMP0 pin and reference voltage COMP0 pin < reference voltage COMP0 pin > reference voltage CDR1 0 1 Result of comparison between COMP1 pin and reference voltage COMP1 pin < reference voltage COMP1 pin > reference voltage Figure 78 Compare Data Register (CDR) 100 HD404669 Series ZTATTM Microcomputer with Built-in Programmable ROM 1. Precautions for use of ZTATTM microcomputer with built-in programmable ROM (1) Precautions for writing to programmable ROM built in ZTATTM microcomputer In the ZTAT TM microcomputer with built-in plastic mold one-time programmable ROM, incomplete electrical connection between the PROM writer and socket adapter causes writing errors and, makes the computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points: (a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it again. (d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing. (f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e). (g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM writer, socket adapter, etc. for defects. (h) If any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) Precautions when new PROM writer, socket adapter or IC is used When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points before starting the writing process. (a) To ensure stable writing operation, check that the VCC of the power supplied to the PROM writer, power source current capacity of VPP, and current consumption at the time of writing to IC are provided with sufficient margin. (b) To prevent breakdown of the IC, check that the power source voltage between GND-V CC and GNDVPP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the pin connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the socket adapter and check the power noise between the GND-VCC and GND-VPP near the IC connecting 101 HD404669 Series terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power sources depending on the noise generated. In case of high frequency noise, insert a capacitor of low inductance. (d) For stable writing and reading operation, insert the IC into the socket adapter and check the input waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent ICs have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. To avoid these problems, inserting a low inductance capacitor between the GND and power source or inserting a damping resistance to the output data terminal is effective. (e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming all ICs inserted into the socket adapter. (f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases due to erroneous writing because of improper connection. Be sure to check the electrical connection between the PROM writer and socket adapter and IC. (g) If any abnormality is noticed while checking a written program, consult our technical staff. 2. Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. PROM mode is set up by setting the TEST, M0, and M1 terminals to "Low" level and the RESET terminal to "High" level. Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256. Using a socket adapter for specific use of each product, programming is possible with a general-purpose PROM writer. Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to write to a 16kword of built-in PROM with a general-purpose PROM writer, specify 32kbyte address ($0000-$7FFF). An example of PROM memory map is shown in figure 80. Notes: 1. When programming with a PROM writer, set up each ROM size to the address given in table 24. If it is programmed erroneously to an address given in Table 24 or later, check of writing of PROM may become impossible. Particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. Set the data in unused addresses to $FF. 2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. Be sure to check that they are properly set to the writer before starting the writing process. 102 HD404669 Series 3. Two levels of program voltages (VPP) are available for the PROM: 12.5 V and 21 V. Our product employs a V PP of 12.5 V. If a voltage of 21 V is applied, permanent breakdown of the product will result. The VPP of 12.5 V is obtained for the PROM writer by setting it according to the Intel 27256 specifications. Writing/verification Programming of the built-in program ROM employs a high speed programming method. With this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. A basic programming flow chart is shown in figure81 and a timing chart in figure82. For precautions for PROM writing procedure, refer to "ZTAT TM Microcomputer On-chip Programmable ROM Characteristics and Usage Notes." Table 23 Selection of Mode Pins Mode Writing Verification Prohibition of programming CE "Low" "High" "High" OE "High" "Low" "High" VPP VPP VPP VPP O0-O4 Data input Data output High impedance Table 24 PROM Writer Program Address ROM size 8k 12k 16k Address $0000~$3FFF $0000~$5FFF $0000~$7FFF 103 HD404669 Series Programmable ROM (HD407A4669) The HD407A4669 is a ZTATTM microcomputer with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description Pin No. FP-64A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MCU Mode Pin Name RE0/VCref TEST OSC1 OSC2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D9 D10 D11 D12 /STOPC D13 /INT0 R00/INT 1 R01/INT 2 R02/INT 3 R03/INT 4 R10 R11 R12 R13 R20 R21 R22 R23 R30 I/O I I I O I I O - I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A5 A6 A7 A8 A0 A10 A11 A12 I I I I I I I I A13 A14 A9 VPP GND GND I I I - - - GND CE OE VCC VCC - I I - - VCC GND - - GND VCC - - PROM Mode Pin Name I/O Pin No. FP-64A 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 MCU Mode Pin Name R33 R32/TOD R31/TOC R40/EVND R41/SCK1 R42/SI1 R43/SO1 R60 R61 R62 R63 R70 R71 R72 R73 R80 R81 R82 R83 R90 R91 R92 R93 RA0 RA1 SEL VCC TONEC TONER VTref RD0/COMP0 RD1/COMP1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I - O O I I I VCC - O4 O3 O2 O1 O0 VCC I/O I/O I/O I/O I/O - A1 A2 A3 A4 O0 O1 O2 O3 O4 I I I I I/O I/O I/O I/O I/O PROM Mode Pin Name I/O 104 HD404669 Series Notes: 1. I/O: I/O pin, I: Input pin, O: Output pin 2. As there are two each of pins O0 to O 4, the respective pairs should be shorted. 3. Unused data pins (O 5 to O 7) on the PROM programmer side should be handled as shown below on the socket side. VCC O5, O6, O7 4. Pin A 9 should be handled as shown below on the socket side. VCC A9 HD407A4669 Programmer side 105 HD404669 Series VCC VCC O0 O1 O2 O3 53 O4 52 51 64 63 62 61 60 59 58 57 56 55 54 50 1 GND VCC 2 3 4 VCC GND 5 6 7 GND CE OE VCC VCC 8 9 10 11 12 13 14 15 A13 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 HD407A4669H FP-64A (Top view) 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 O4 O3 O2 O1 O0 A4 A3 A2 A1 GND GND VPP A14 A10 A11 Figure 79 Pin Arrangement in PROM Mode 106 A12 A5 A6 A9 A7 A8 A0 HD404669 Series $0000 $0001 . . . $001F $0020 . . . $007F $0080 . . . $1FFF $2000 1 1 1 1 1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Lower 5 bits Upper 5 bits $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) $0FFF $1000 Program (16,384 words) JMPL instruction (jump to RESET, STOPC routine) JMPL instruction (jump to INT 0 routine) JMPL instruction (jump to INT 1 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to INT2 routine) JMPL instruction (jump to timer C, INT3 routine) JMPL instruction (jump to timer D, INT4 routine) JMPL instruction (jump to serial 1 routine) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $7FFF $3FFF Upper three bits are not to be used (fill them with 111) Figure 80 Memory Map in PROM Mode 107 HD404669 Series Start Set write/verify modes V CC = 6.0 0.25 V, V PP = 12.5 0.3 V Address = 0 n=0 n + 1 n Program t PW =1 ms 5% Yes No n < 25? No Verification OK? Yes Program t OPW = 3n ms Address + 1 Address Last address? Yes VCC No Set read mode = 5.0 0.5 V, V PP = V CC 0.6 V Reject No Read all addresses ? Yes End Figure 81 Flowchart of High-Speed Programming 108 HD404669 Series Programming Electrical Characteristics DC Characteristics (VCC = 6.0 V 0.25 V, V PP = 12.5 V 0.3 V, GND = 0V, Ta = 25C 5C, unless otherwise specified) Item Input high voltage level Input low voltage level Output high voltage level Output low voltage level Input leakage current VCC current VPP current Pin(s) O0-O4, A0-A14, OE, CE O0-O4, A0-A14, OE, CE O0-O4 O0-O4 O0-O4, A0-A14, OE, CE Symbol VIH VIL VOH VOL I IL I CC I PP Min 2.2 -0.3 2.4 -- -- -- -- Typ -- -- -- -- -- -- -- Max VCC + 0.3 0.8 -- 0.4 2 30 40 Unit V V V V A mA mA I OH = -200 A I OL = 1.6 mA Vin = 5.25 V/0.5 V Test Condition AC Characteristics (VCC = 6.0 V 0.25 V, V PP = 12.5 V 0.3 V, GND = 0V, Ta = 25C 5C, unless otherwise specified) Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Program pulse width CE pulse width during overprogramming VCC setup time Data output delay time Symbol t AS t OES t DS t AH t DH t DF t VPS t PW t OPW t VCS t OE Min 2 2 2 0 2 -- 2 0.95 2.85 2 0 Typ -- -- -- -- -- -- -- 1.0 -- -- -- Max -- -- -- -- -- 130 -- 1.05 78.75 -- 500 Unit s s s s s ns s ms ms s ns Test Condition See figure 82 Note: Input pulse level: 0.8 V to 2.2 V Input rise/fall time: 20 ns Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V 109 HD404669 Series Address Write Verify tAS Data Data In Stable tAH Data Out Valid tDS VPP VPP GND VCC CE VCC GND tDH tDF tVPS tVCS tPW OE tOES tOE tOPW Figure 82 PROM Write/Verify Timing 110 HD404669 Series ZTATTM Microcomputer Usage Notes ZTATTM Microcomputer On-Chip Programmable ROM Characteristics and Useage Notes Principles of Programming/Erasure: A memory cell in a ZTATT M microcomputer is the same as an EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an SiO 2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0. The charge in a memory cell may decrease with time. This decrease is usually due to one of the following causes: * Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure principle. * Heat excites trapped electrons, allowing them to escape. * High voltages between the control gate and drain may erase electrons. If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However, electron erasure does not often occur because defective devices are detected and removed at the testing stage. Control gate SiO2 Source N+ N+ SiO2 Floating gate Drain Source N+ N+ Floating gate Drain Control gate Write (0) Erasure (1) Figure 83 Cross-Sections of a PROM Cell PROM Programming: PROM memory cells must be programmed under specific voltage and timing conditions. The higher the programming voltage VPP and the longer the programming pulse t PW is applied, the more electrons are injected into the floating gates. However, if V PP exceeds specifications, the pn junctions may be permanently damaged. Pay particular attention to overshooting in the PROM programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. The ZTAT TM microcomputer is electrically connected to the PROM programmer by a socket adapter. Therefore, note the following points: 111 HD404669 Series * Check that the socket adapter is firmly mounted on the PROM programmer. * Do not touch the socket adapter or the LSI during the programming. Touching them may affect the quality of the contacts, which will cause programming errors. PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure section.) ZTAT TM microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but Hitachi recommends that each device be exposed to 150C at one atmosphere after it is programmed, to ensure its best performance. The recommended screening procedure is shown in figure 84. Write the program data and verify the values written Expose to high temperature, without power 150C 10C, 48 h +8 h * -0 h Program read check VCC = 4.5 V or 5.5 V Note: * Exposure time is measured from when the temperature in the heater reaches 150C. Figure 84 Recommended Screening Procedure Note: If programming errors occur continuously during PROM programming, suspend programming and check for problems in the PROM programmer or socket adapter, using a windowed-package microcomputer with on-chip EPROM, etc. ..... If programming verification indicates errors in programming or after high-temperature exposure, please inform Hitachi. Write rate: A write rate of 95% or above is guaranteed. 112 HD404669 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 85 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. For $090 to $25F, a bank setting must be made in the bank register (V: $03F). Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. W register W1 W0 X3 X register X2 X1 X0 Y3 Y register Y2 Y 1 Y0 RAM address AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Indirect Addressing 1st word of Instruction Opcode d 9 2nd word of Instruction d8 d7 d6 d5 d4 d3 d2 d1 d0 RAM address AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 0 0 1 0 0 m3 m2 m1 m0 RAM address AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 85 RAM Addressing Modes 113 HD404669 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 86 and described below. 1st word of instruction Opcode p3 p2 p1 p0 d9 d8 2nd word of instruction d7 d6 d5 d4 d3 d2 d1 d0 [JMPL] [BRL] [CALL] Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 0 Opcode 0 0 0 d5 d4 d3 d2 d1 d0 Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 B2 B1 B0 A3 Accumulator A2 A1 A0 0 Program counter 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 86 ROM Addressing Modes 114 HD404669 Series Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC 7-PC0) with eight-bit immediate data. A branch by a BR instruction located at a page boundary differs from other cases: see figure 88. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 88. If bit 8 of the ROM data is 1, the lower eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, the lower eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. Branch destination of a BR instruction on a page boundary: When a BR instruction is on a page boundary (256n + 255), the program counter will advance to the next page because of the hardware architecture. Therefore, when using a BR instruction on a page boundary, the branch destination should be set in the next page (see figure 88). HMCS400 Series cross assemblers are provided with an automatic paging function that automatically turns the ROM page, irrespective of the model. 115 HD404669 Series Instruction [P] Opcode p3 p2 p1 p0 B3 0 0 B register B2 B1 B0 A3 Accumulator A2 A1 A0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 Pattern Output If RO 9 = 1 Figure 87 P Instruction 256 (n - 1) + 255 BR AAA 256n AAA NOP BR BR AAA BBB 256n + 254 256n + 255 256 (n + 1) BBB NOP Figure 88 Branching when the Branch Destination is on a Page Boundary 116 HD404669 Series Instruction Set The MCU has 101 instructions, classified into the following 10 groups: * * * * * * * * * * Immediate instructions Register-to-register instructions RAM addressing instructions RAM register instructions Arithmetic instructions Compare instructions RAM bit manipulation instructions ROM addressing instructions Input/output instructions Control instructions The functions of these instructions are listed in tables 25 to 34, and an opcode map is shown in table 35. Table 25 Immediate Instructions Words/ Cycles 1/1 1/1 2/2 NZ 1/1 Operation Load A from immediate Load B from immediate Load memory from immediate Load memory from immediate, increment Y Mnemonic LAI i LBI i LMID i,d LMIIY i Operation Code 1 0 0 0 1 1 i3 i2 i1 i0 1 0 0 0 0 0 i3 i2 i1 i0 0 1 1 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 0 0 1 i3 i2 i1 i0 Function iA iB iM i M, Y + 1 Y Status 117 HD404669 Series Table 26 Register-Register Instructions Words/ Cycles 1/1 1/1 2/2* 1/1 1/1 1/1 1/1 1/1 Operation Load A from B Load B from A Load A from W Load A from Y Load A from SPX Load A from SPY Load A from MR Exchange MR and A Mnemonic LAB LBA LAW LAY LASPX LASPY LAMR m XMRA m Operation Code 0001001000 0011001000 0100000000 0000000000 0010101111 0001101000 0001011000 1 0 0 1 1 1 m3 m2 m1 m0 1 0 1 1 1 1 m3 m2 m1 m0 Function BA AB WA YA SPX A SPY A MR (m) A MR (m) A Status Note: * The assembler automatically provides an operand for the second word of the LAW instruction. Table 27 RAM Address Instructions Status Operation Load W from immediate Load X from immediate Load Y from immediate Load W from A Load X from A Load Y from A Increment Y Decrement Y Add A to Y Subtract A from Y Exchange X and SPX Exchange Y and SPY Exchange X and SPX, Y and SPY Mnemonic LWI i LXI i LYI i LWA LXA LYA IY DY AYY SYY XSPX XSPY XSPXY Operation Code 0 0 1 1 1 1 0 0 i1 i0 1 0 0 0 1 0 i3 i2 i1 i0 1 0 0 0 0 1 i3 i2 i1 i0 0100010000 0000000000 0011101000 0011011000 0001011100 0011011111 0001010100 0011010100 0000000001 0000000010 0000000011 Function iW iX iY AW AX AY Y+1Y Y-1Y Y+AY Y-AY X SPX Y SPY X SPX,Y SPY NZ NB OVF NB Words/ Cycles 1/1 1/1 1/1 2/2* 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 Note: * The assembler automatically provides an operand for the second word of the LWA instruction. 118 HD404669 Series Table 28 RAM Register Instructions Words/ Cycles 1/1 2/2 1/1 1/1 2/2 NZ NB 1/1 1/1 1/1 2/2 1/1 Operation Load A from memory Load A from memory Load B from memory Load memory from A Load memory from A Load memory from A, increment Y Load memory from A, decrement Y Exchange memory and A Exchange memory and A Exchange memory and B Mnemonic LAM(XY) LAMD d LBM(XY) LMA(XY) LMAD d LMAIY(X) LMADY(X) XMA(XY) XMAD d XMB(XY) Operation Code 00100100y x Function MA (X SPX, Y SPY) MA MB (X SPX, Y SPY) AM (X SPX, Y SPY) AM A M, Y + 1 Y (X SPX) A M, Y - 1 Y (X SPX) MA (X SPX, Y SPY) MA MB (X SPX, Y SPY) Status 0110010000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00010000y 00100101y x x 0110010100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000101000x 001101000x 00100000y x 0110000000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00110000y x Note: The meanings of (XY) and (X) are as follows: Each instruction marked with (XY) has 4 mnemonics, each with different object codes. For example, different values of x and y of the opcode of the LAM(XY) instruction are given below. Mnemonic LAM LAMX LAMY LAMXY y 0 0 1 1 x 0 1 0 1 Function None X SPX Y SPY X SPX, Y SPY Each instruction marked with (X) has 2 mnemonics, each with different object codes. For example, different values of x of the opcode of the LMAIY(X) instruction are given below. Mnemonic LMAIY LMAIYX x 0 1 Function None X SPX 119 HD404669 Series Table 29 Arithmetic Instructions Words/ Cycles 1/1 1/1 1/1 1/1 1/1 A+1A B B 1/1 1/1 1/1 1/1 1 CA 0 CA CA M+AA M+AA M + A + CA A OVF CA M + A + CA A OVF CA M - A - CA A NB CA M - A - CA A NB CA ABA AMA AMA AMA AMA AMA AMA NZ NZ NZ NZ NZ NZ OVF OVF OVF OVF NB NB 1/1 1/1 1/1 1/1 2/2 1/1 2/2 1/1 2/2 1/1 1/1 2/2 1/1 2/2 1/1 2/2 Operation Add immediate to A Increment B Decrement B Decimal adjust for addition Decimal adjust for subtraction Negate A Complement B Rotate right A with carry Rotate left A with carry Set carry Reset carry Test carry Add A to memory Add A to memory Add A to memory with carry Add A to memory with carry Subtract A from memory with carry Subtract A from memory with carry OR A and B AND memory with A AND memory with A OR memory with A OR memory with A EOR memory with A EOR memory with A Mnemonic AI i IB DB DAA DAS NEGA COMB ROTR ROTL SEC REC TC AM AMD d AMC AMCD d SMC SMCD d OR ANM ANMD d ORM ORMD d EORM EORMD d Operation Code 1 0 1 0 0 0 i3 i2 i1 i0 0001001100 0011001111 0010100110 0010101010 0001100000 0101000000 0010100000 0010100001 0011101111 0011101100 0001101111 0000001000 0100001000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000011000 0100011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0010011000 0110011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0101000100 0010011100 0110011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000001100 0100001100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000011100 0100011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Function A+iA B+1B B-1B Status OVF NZ NB 120 HD404669 Series Table 30 Compare Instructions Words/ Cycles 1/1 2/2 1/1 2/2 1/1 1/1 1/1 2/2 1/1 2/2 1/1 1/1 Operation Immediate not equal to memory Immediate not equal to memory A not equal to memory A not equal to memory B not equal to memory Y not equal to immediate Immediate less than or equal to memory Immediate less than or equal to memory A less than or equal to memory A less than or equal to memory B less than or equal to memory A less than or equal to immediate Mnemonic INEM i INEMD i,d ANEM ANEMD d BNEM YNEI i ILEM i ILEMD i,d ALEM ALEMD d BLEM ALEI i Operation Code 0 0 0 0 1 0 i3 i2 i1 i0 0 1 0 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000100 0100000100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0001000100 0 0 0 1 1 1 i3 i2 i1 i0 0 0 0 0 1 1 i3 i2 i1 i0 0 1 0 0 1 1 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000010100 0100010100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0011000100 1 0 1 0 1 1 i3 i2 i1 i0 Function iM iM AM AM BM Yi iM iM AM AM BM Ai Status NZ NZ NZ NZ NZ NZ NB NB NB NB NB NB Table 31 RAM Bit Manipulation Instructions Operation Set memory bit Set memory bit Reset memory bit Reset memory bit Test memory bit Test memory bit Words/ Cycles 1/1 2/2 1/1 2/2 M (n) M (n) 1/1 2/2 Mnemonic SEM n SEMD n,d REM n REMD n,d TM n TM n,d Operation Code 0 0 1 0 0 0 0 1 n1 n0 0 1 1 0 0 0 0 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 0 1 0 n1 n0 0 1 1 0 0 0 1 0 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 0 1 1 n1 n0 0 1 1 0 0 0 1 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Function 1 M (n) 1 M (n) 0 M (n) 0 M (n) Status 121 HD404669 Series Table 32 ROM Address Instructions Words/ Cycles 1/1 2/2 2/2 1 1 1 1/2 2/2 1/1 1/3 1 IE, carry restored ST 1/3 Operation Branch on status 1 Long branch on status 1 Long jump unconditionally Subroutine jump on status 1 Long subroutine jump on status 1 Table branch Return from subroutine Return from interrupt Mnemonic BR b BRL u JMPL u CAL a CALL u TBR p RTN RTNI Operation Code 1 1 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 1 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 1 a5 a4 a3 a2 a1 a0 0 1 0 1 1 0 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1 1 p3 p2 p1 p0 0000010000 0000010001 Function Status 1 1 Table 33 Input/Output Instructions Words/ Cycles 1/1 1/1 1/1 1/1 D (Y) D (m) R (m) A R (m) B A R (m) B R (m) 1/1 1/1 1/1 1/1 1/1 1/1 1/2 Operation Set discrete I/O latch Set discrete I/O latch direct Reset discrete I/O latch Reset discrete I/O latch direct Test discrete I/O latch Test discrete I/O latch direct Load A from R-port register Load B from R-port register Load R-port register from A Load R-port register from B Pattern generation Mnemonic SED SEDD m RED REDD m TD TDD m LAR m LBR m LRA m LRB m Pp Operation Code 0011100100 1 0 1 1 1 0 m3 m2 m1 m0 0001100100 1 0 0 1 1 0 m3 m2 m1 m0 0011100000 1 0 1 0 1 0 m3 m2 m1 m0 1 0 0 1 0 1 m3 m2 m1 m0 1 0 0 1 0 0 m3 m2 m1 m0 1 0 1 1 0 1 m3 m2 m1 m0 1 0 1 1 0 0 m3 m2 m1 m0 0 1 1 0 1 1 p3 p2 p1 p0 Function 1 D (Y) 1 D (m) 0 D (Y) 0 D (m) Status 122 HD404669 Series Table 34 Control Instructions Words/ Cycles 1/1 1/1 1/1 1/1 Operation No operation Start serial Standby mode/watch mode* Stop mode/watch mode Mnemonic NOP STS SBY STOP Operation Code 0000000000 0101001000 0101001100 0101001101 Function Status Note: * Only after a transition from subactive mode. 123 HD404669 Series Table 35 Opcode Map R8 R9 H 0 1 2 3 4 5 6 0 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 8 9 A B C D E F 1-word/2-cycle instruction 1-word/3-cycle instruction TD LWI i(2) LBI i(4) LYI i(4) LXI i(4) LAI i(4) LBR m(4) LAR m(4) REDD m(4) LAMR m(4) AI i(4) LMIIY i(4) TDD m(4) ALEI i(4) LRB m(4) LRA m(4) SEDD m(4) XMRA m(4) XMB(XY) LMADY(X) BLEM SYY SED XMA(XY) LAM(XY) ROTR ROTL SEM n(2) LMA(XY) DAA TBR p(4) LBA LYA LXA REC DB DY SEC SMC DAS NEGA LBM(XY) LMAIY(X) BNEM AYY RED 0 0 NOP RTN L 1 RTNI 2 3 4 ALEM 5 6 7 8 AM AMC 9 A B C ORM EORM D E F XSPX XSPY XSPXY ANEM INEM i(4) ILEM i(4) LAB LASPY LASPX YNEI i(4) REM n(2) ANM LAY TM n(2) IB IY TC RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 124 HD404669 Series R8 R9 H 0 1 2 3 4 5 6 0 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 8 9 A B C D E F 1-word/2-cycle instruction 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction BR b(8) CAL a(6) XMAD LAMD LMAD SEMD n(2) SMCD LMID i(4) P p(4) COMB OR 1 0 LAW LWA L 1 2 3 4 ANEMD ALEMD 5 6 7 8 AMD AMCD 9 A B C ORMD EORMD D E F INEMD i(4) ILEMD i(4) STS JMPL p(4) CALL p(4) BRL p(4) REMD n(2) ANMD TMD n(2) SBY STOP 125 HD404669 Series Absolute Maximum Ratings Item Supply voltage Programming voltage Pin voltage Total permissible input current (to chip) Total permissible output current (from chip) Maximum input current (to chip) Symbol VCC VPP VT Io -Io Io -I o Topr Tstg Value -0.3 to +7.0 -0.3 to +14.0 -0.3 to (VCC + 0.3) 100 50 4 30 Maximum output current (from chip) 4 20 Operating temperature Storage temperature -20 to +75 -55 to +125 Unit V V V mA mA mA mA mA mA C C 2 3 4, 5 4, 6 7, 8 7, 9 10 11 1 Notes Notes: 1. Applies to D 13 (VPP) of the HD407A4669. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to D 0-D 3, R0-R4 and R6-RA. 6. Applies to D 4, D5 and D 9-D 11 7. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 8. Applies to D 4, D5, D9-D 11, R0-R4 and R6-RA. 9. Applies to D 0-D 3. 10. The operating temperature indicates the temperature range in which power can be supplied to the LSI (voltage V CC shown in the electrical characteristics tables can be applied). 11. In the case of chips, the storage specification differs from that of the package products. Please consult your Hitachi sales representative for details. Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 126 HD404669 Series Electrical Characteristics DC Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = -20C to +75C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, T a = +75C; HD407A4669: V CC = 2.2 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Input high voltage Symbol VIH Pin(s) RESET, SCK1, SI 1, INT0, INT1, INT2, INT3, INT4, STOPC, EVND OSC1 RESET, SCK1, SI 1, INT0, INT1, INT2, INT3, INT4, STOPC, EVND OSC1 SCK 1, SO1, TOC, TOD SCK 1, SO1, TOC, TOD RESET, SCK1, SI 1, INT0, INT1, INT2, INT3, INT4, STOPC, EVND, OSC1, SO 1, TOC, TOD VCC Min 0.9VCC Typ -- Max VCC + 0.3 Unit V Test Condition -- Notes VCC - 0.3 -0.3 -- -- VCC + 0.3 0.10VCC V V Input low voltage VIL External clock operation -- -0.3 VCC - 0.5 -- -- -- -- -- -- 0.3 -- 0.4 1.0 V V V A Output high voltage Output low voltage I/O leakage current VOH VOL II L External clock operation -I OH = 0.3 mA IOL = 0.4 mA Vin = 0 V to V CC 1 Active mode current dissipation (digital input mode) ICC1 -- 2.5 5.0 mA VCC = 5.0 V, fOSC = 4 MHz 2 ICC2 ICC3 VCC VCC -- -- 0.3 5.0 1.0 9.0 mA mA VCC = 3.0 V, fOSC = 800 kHz HD40A4668, HD40A46612, HD40A4669, HD407A4669: VCC = 5 V, fOSC = 8 MHz 2 2 127 HD404669 Series Item Active mode current dissipation (analog compare mode) Symbol ICMP1 Pin(s) VCC Min -- Typ 6.5 Max 9.0 Unit mA Test Condition VCC = 5V, fOSC = 4MHz Notes 3 ICMP2 ICMP3 VCC VCC -- -- 2.8 9.0 3.5 13.0 mA mA Standby mode current dissipation ISBY1 VCC -- 1.0 2.0 mA VCC = 3V, fOSC = 800kHz HD40A4668, HD40A46612, HD40A4669, HD407A4669: VCC = 5V, fOSC = 8MHz VCC = 5V, fOSC = 4MHz 3 3 4 ISBY2 ISBY3 VCC VCC -- -- 0.1 2.0 0.3 4.0 mA mA Subactive mode current dissipation Watch mode current dissipation Stop mode current dissipation Stop mode retention voltage Comparator input reference voltage range ISUB VCC -- 18 35 A VCC = 3V, fOSC = 800kHz HD40A4668, HD40A46612, HD40A4669, HD407A4669: VCC = 5V, fOSC = 8MHz VCC = 3 V, 32 kHz oscillator used VCC = 3 V, 32 kHz oscillator used VCC = 3 V, no 32 kHz oscillator No 32 kHz oscillator 4 4 5 IWTC VCC -- 4 7.5 A 5 ISTOP VCC -- 0.5 5 A 5 VSTOP VCC 1.5 -- -- V 6 VCref VCref 0 -- VCC--1.2 V Notes: 1. Output buffer current is excluded. 2. Power supply current when the MCU is in the reset state and there are no I/O currents. Test conditions: MCU: Pins: Reset RESET at V CC (VCC - 0.3 V to VCC) TEST at V CC (VCC - 0.3 V to VCC) 3. Power supply current when pins RD0 and RD1 are in analog input mode and there are no I/O currents. Test conditions: MCU: DTMF not operating Pins: * RD 0/COMP0: At GND (0 V to 0.3 V) * RD 1/COMP1: At GND (0 V to 0.3 V) * RE0/VCref: At GND (0 V to 0.3 V) 128 HD404669 Series 4. Power supply current when the on-chip timers are operating and there are no I/O currents. Test conditions: MCU: I/O reset Serial interface stopped DTMF not operating Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC - 0.3 V to VCC) 5. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC - 0.3 V to VCC) D13 at V CC (VCC - 0.3 V to VCC) for the HD407A4669 6. The required voltage for RAM data retention. 129 HD404669 Series I/O Characteristics for Standard Pins (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = -20C to +75C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Input high voltage Input low voltage Output high voltage Output low voltage I/O leakage current Symbol VIH Pin(s) D12 , D13 , R0 to R4, R6 to RA, RD, RE0 D12 , D13 , R0 to R4, R6 to RA, RD, RE0 R0 to R4, R6 to RA R0 to R4, R6 to RA D12 , R0 to R4, R6 to RA, RD, RE0 D13 Min 0.7VCC Typ -- Max VCC + 0.3 Unit V Test Condition -- Notes VIL -0.3 -- 0.3VCC V -- VOH VOL II L VCC - 0.5 -- -- -- -- -- -- 0.4 1 V V A -I OH = 0.3 mA IOL = 0.4 mA Vin = 0 V to V CC 1 -- -- 1 A HD404668, HD4046612, HD404669, HCD404669, HD40A4668, HD40A46612, HD40A4669: Vin = 0V to V CC HD407A4669: Vin = VCC - 0.3V to VCC HD407A4669: Vin = 0V to 0.3V VCC = 3.0 V, Vin = 0 V Analog compare mode Analog compare mode 1 -- -- 1 A 1 -- Pull-up MOS current Input high voltage Input low voltage -I PU VIHA VILA R0 to R4, R6 to RA COMP0, COMP1 COMP0, COMP1 10 -- 50 -- -- 20 150 -- A A V V 1 VC ref +0.1 -- VC ref - 0.1 Note: 1. Output buffer current is excluded. 130 HD404669 Series I/O Characteristics for High-Current (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VC C = 1.8 to 5.5 V, GND = 0 V, T a = -20C to +75C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Input high voltage Input low voltage Output high voltage Symbol VIH VIL VOH Pin(s) D0 to D5, D9 to D11 D0 to D5, D9 to D11 D0 to D5, D9 to D11 D0 to D3 Output low voltage VOL Min 0.7VCC -0.3 VCC - 0.5 VCC - 2.0 Typ -- -- -- -- Max VCC + 0.3 0.3VCC -- -- Unit V V V V Test Condition -- -- -I OH = 0.3 mA -I OH = 10 mA VCC = 4.5V to 5.5V D0 to D5, D9 to D11 D4, D5, D9 to D11 I/O leakage current Pull-up MOS current Pull-down MOS current II L -I PU IPD D0 to D5, D9 to D11 D4, D5, D9 to D11 D0 to D3 -- -- -- 10 10 -- -- -- 50 50 0.4 2.0 1 150 150 V V A A A IOL = 0.4 mA IOL = 15 mA, VCC = 4.5 V to 5.5 V Vin = 0 V to V CC VCC = 3 V, Vin = 0 V VCC = 3 V, Vin = 3 V 1 Notes Note: 1. Output buffer current is excluded. 131 HD404669 Series DTMF Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = -20C to +75C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Tone output voltage (1) Tone output voltage (2) Tone output distortion Symbol VOR Pin TONER Min 500 Typ 660 Max -- Unit mVr ms Test Condition VTref - GND = 2.0 V, R L = 100 k, VCC = 2.2 to 5.0V VTref - GND = 2.0 V, R L = 100 k, VCC = 2.2 to 5.0V Short circuit between TONER and TONEC, R L = 100 k Short circuit between TONER and TONEC, R L = 100 k Notes 1 VOC TONEC 520 690 -- mVr ms 1 %DIS -- -- 3 7 % 2 Tone output ratio dBCR -- -- 2.5 -- dB 2 Notes: These characteristics are guaranteed with an operating frequency, fOSC, of 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz, or 8 MHz. 1. See figure 89. 2. See figure 90. 132 HD404669 Series AC Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = -20C to +75C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) Item Clock oscillation frequency Symbol fOSC Pin(s) OSC1, OSC2 Min -- -- -- -- -- -- Typ 400 800 2 3.58 4 7.16 Max -- -- -- -- -- -- Unit kHz kHz MHz MHz MHz MHz HD40A4668, HD40A46612, HD40A4669, HD407A4669: VCC = 4.0V to 5.5V Test Condition Notes 1 1 1 1 1 1 -- X1, X2 Instruction cycle time tcyc -- -- -- -- -- -- tsubcyc -- -- -- Oscillation stabilization time (ceramic oscillator) Oscillation stabilization time (crystal oscillator) tRC OSC1, OSC2 -- 8 32.768 8 4 2 1 244.14 122.07 -- -- -- -- -- -- -- -- -- 7.5 MHz kHz s s s s s s ms fOSC = 4 MHz, division by 32 fOSC = 4 MHz, division by 16 fOSC = 4 MHz, division by 8 fOSC = 4 MHz, division by 4 32 kHz oscillator used, division by 8 32 kHz oscillator used, division by 4 2 2 2 2 3 3 4, 5 tRC OSC1, OSC2 X1, X2 -- -- 1100 550 215 115 105 57.5 52.5 -- -- -- -- -- -- -- -- -- 30 2 -- -- -- -- -- -- -- ms s ns ns ns ns ns ns ns Ta = -10C to +60C fOSC = 400 kHz fOSC = 800 kHz fOSC = 2 MHz fOSC = 3.58 MHz fOSC = 4 MHz fOSC = 7.16 MHz fOSC = 8 MHz 4, 5, 12 4 6 External clock high width tCPH OSC1 6, 11 133 HD404669 Series Item External clock low width Symbol tCPL Pin(s) OSC1 Min 1100 550 215 115 105 57.5 52.5 External clock rise time tCPr OSC1 -- -- -- -- -- -- -- External clock fall time tCPf OSC1 -- -- -- -- -- -- -- INT0-INT4, EVND high widths INT0-INT4, EVND low widths RESET high width STOPC low width RESET fall time STOPC rise time Input capacitance tI H tI L tRSTH tSTPL tRSTf tSTPr Cin INT0 to INT4, EVND INT0 to INT4, EVND RESET STOPC RESET STOPC All pins except D 13 D13 2 2 2 1 -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- 150 75 35 25 20 12.5 10 150 75 35 25 20 12.5 10 -- -- -- -- 20 20 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tcyc / tsubcyc tcyc / tsubcyc tcyc tRC ms ms pF pF -- -- -- -- f = 1 MHz Vin = 0 V, HD40A4668, HD40A46612, HD40A4669, HCD404669, HD404668, HD4046612, HD404669: f = 1MHz, Vin = 0V HD407A4669: f = 1MHz, Vin = 0V 8 9 8 9 -- 7 Test Condition fOSC = 400 kHz fOSC = 800 kHz fOSC = 2 MHz fOSC = 3.58 MHz fOSC = 4 MHz fOSC = 7.16 MHz fOSC = 8 MHz fOSC = 400 kHz fOSC = 800 kHz fOSC = 2 MHz fOSC = 3.58 MHz fOSC = 4 MHz fOSC = 7.16 MHz fOSC = 8 MHz fOSC = 400 kHz fOSC = 800 kHz fOSC = 2 MHz fOSC = 3.58 MHz fOSC = 4 MHz fOSC = 7.16 MHz fOSC = 8 MHz -- 7 6, 11 6 6, 11 6 6, 11 Notes 6 -- -- 40 pF 134 HD404669 Series Item Analog comparator stabilization time Symbol tCSTB Pin(s) COMP0 to COMP1 Min -- -- Typ -- -- Max 2 10 Unit tcyc tcyc Test Condition VCC = 2.2 V to 5.5V VCC = 1.8 V to less than 2.2V Notes 10 Notes: 1. Set bits 0 and 1 (SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22, SSR23) of system clock select register 2 (SSR2: $02A) according to the system clock frequency used. 2. Set bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2: $02A) according to the system clock frequency division ratio used. 3. Set bit 2 (SSR12) of system clock select register 1 (SSR1: $029) according to the subsystem clock frequency division ratio used. 4. The oscillation stabilization time is defined as follows: (1) The time required for the oscillation to settle after VCC has reached the minimum specification value at power-on. (2) The time required for the oscillation to settle after RESET input has gone high when stop mode is cleared. (3) The time required for the oscillation to settle after STOPC input has gone low when stop mode is cleared. To ensure enough time for the oscillation to settle at power-on or when stop mode is cleared, input the RESET or STOPC signal for at least time tRC. The oscillation stabilization time will depend on the circuit constants and stray capacitance. The oscillator should be determined in consultation with the oscillator manufacturer. 5. Set bits 0 and 1 (MIS0, MIS1) in the miscellaneous register (MIS: $00C) according to the oscillation stabilization time of the system oscillator. 6. See figure 91. 7. See figure 92. Unit tcyc applies when the MCU is in standby mode or active mode. Unit tsubcyc applies when the MCU is in watch mode or subactive mode. 8. See figure 93. 9. See figure 94. 10. This is the time required for the analog comparator to settle, ensuring that the correct data is read, after pins RD 0 /COMP0 and RD1/COMP1 are set to analog input mode. 11. Applies to the HD40A4668, HD40A46612, HD40A4669, and HD407A4669. The test condition is VCC = 4.0 to 5.5 V. 12. Applies to the HD404668, HD4046612, HD404669, HCD404669, HD40A4668, HD40A46612, and HD40A4669. The test condition is VCC = 2.0 to 5.5 V. 135 HD404669 Series Serial Interface Timing Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: VCC = 1.8 to 5.5 V, GND = 0 V, T a = -20C to +75C; HCD404669: VCC = 1.8 to 5.5 V, GND = 0 V, Ta = +75C; HD407A4669: VCC = 2.2 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) During Transmit Clock Output Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Transmit clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Symbol tScyc tSCKH tSCKL tSCKr tSCKf tDSO tSSI tHSI Pin SCK1 SCK1 SCK1 SCK1 SCK1 SO 1 SI 1 SI 1 Min 1.0 0.4 0.4 -- -- -- 200 200 Typ -- -- -- -- -- -- -- -- Max -- -- -- 100 100 300 -- -- Unit tcyc tScyc tScyc ns ns ns ns ns Test Condition Load shown in figure 96 Load shown in figure 96 Load shown in figure 96 Load shown in figure 96 Load shown in figure 96 Load shown in figure 96 -- -- Notes 1 1 1 1 1 1 1 1 Note: 1. Refer to figure 95. During Transmit Clock Input Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Transmit clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Symbol tScyc tSCKH tSCKL tSCKr tSCKf tDSO tSSI tHSI Pin SCK1 SCK1 SCK1 SCK1 SCK1 SO 1 SI 1 SI Min 1.0 0.4 0.4 -- -- -- 200 200 Typ -- -- -- -- -- -- -- -- Max -- -- -- 100 100 300 -- -- Unit tcyc tScyc Test Condition -- -- -- -- -- Load shown in figure 96 -- -- Notes 1 1 1 1 1 1 1 1 tScyc ns ns ns ns ns 1 Note: 1. Refer to figure 95. 136 HD404669 Series RL = 100 k TONEC GND TONER RL = 100 k Figure 89 Tone Output Load Circuit TONEC RL = 100 k GND TONER Figure 90 Distortion and dBCR Load Circuit OSC1 1/fCP VCC - 0.3 V 0.3 V tCPr tCPH tCPf tCPL Figure 91 External Clock Timing INT0 to INT4, EVND 0.9 VCC 0.1 VCC tIH tIL Figure 92 Interrupt Timing 137 HD404669 Series RESET 0.9 VCC 0.1 VCC tRSTH tRSTf Figure 93 Reset Timing STOPC 0.9 VCC 0.1 VCC tSTPL tSTPr Figure 94 STOPC Timing tScyc tSCKf VCC - 0.5 V (0.9 VCC) * SCK1 0.4 V (0.1 VCC) * tSCKr tSCKL tSCKH tDSO VCC - 0.5 V 0.4 V tSSI 0.9 VCC 0.1VCC tHSI SO1 SI1 Note: * VCC - 0.5 V and 0.4 V are the threshold voltages during serial clock output. 0.9 VCC and 0.1 VCC are the threshold voltages during serial clock input. Figure 95 Serial Interface Timing 138 HD404669 Series VCC RL = 2.6 k Test point C = 30 pF R = 12 k 1S2074 H or equivalent Figure 96 Timing Load Circuit 139 HD404669 Series Notes on ROM Out Please note the following when ordering HD404668, HD4046612, HD40A4668, or HD40A46612 ROM. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404669, HD40A4669). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base. 8-kword ROM versions: HD404668, HD40A4668 Write all-1 data to addresses $2000 to $3FFF. $0000 Vector addresses $000F $0010 Zero page subroutine area (64 words) $000F $0010 $0000 Vector addresses Zero page subroutine area (64 words) 12-kword ROM versions: HD4046612, HD40A46612 Write all-1 data to addresses $3000 to $3FFF. $003F $0040 $003F $0040 Program and pattern area (8,192 words) $1FFF $2000 $2FFF $3000 Not used Program and pattern area (12,288 words) Not used $3FFF $3FFF Note: Write all-1 data in shaded areas. 140 HD404669 Series HD404668/HD4046612/HD404669/HCD404669/HD40A4668/HD40A46612/HD40A4669 Option List Please check off the appropriate applications and enter the necessary information. Date of order Customer Department Name ROM code name LSI number (Hitachi entry) / / 1. ROM Size Standard operation version: HD404668 High-speed operation version: HD40A4668 Standard operation version: HD4046612 High-speed operation version: HD40A46612 Standard operation version: HD404669 High-speed operation version: HD40A4669 Chip version: HCD404669 16-kword 12-kword 8-kword 2. Optional Functions * * Note: * With 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base for clock Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM Code Data Type Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMs 4. System Oscillator (OSC 1 and OSC2) Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz 5. Stop Mode Used Not used 6. Package FP-64A Chip Note: The specifications of shipped chips differ from of the package product. Please contact our sales staff for details. 141 HD404669 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 142 |
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